Lp trnh VHDL

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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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I. Gii thiu VHDL L ngn ng m phng v tng hp phn cng

VHSIC Hardware Description Language VHSIC = Very High Speed IC

ng dng
PLD (Programmable Logic Device)
CPLD (Complex PLD) FPGA (Field Programmable Gate Array)

ASIC (Application-Specific IC)

Cng c
Xilinx ISE v Altera Quartus
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I. Gii thiu VHDL (tip) c im ngn ng

Khng phn bit ch hoa thng Cc lnh c phn cch bi du ; Cc ch thch c bt u bi du --
M phng phn cng theo hng Top-down Yu cu cht ch v kiu d liu

Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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II. Cu trc Library

Library cha cc php ton c xy dng sn trn 1 kiu d liu no .

Entity
Entity th hin giao din bn ngoi ca vi mch (cc cng vo/ra).

Architecture
Architecture th hin cu trc bn trong, chc nng, hot ng ca vi mch.

II. Cu trc (tip)

LIBRARY IEEE; USE ...; -------------------ENTITY Example IS GENERIC (...); PORT (...); END Example; -------------------ARCHITECTURE Ex1 OF Example IS COMPONENT (...); GENERIC MAP (...); PORT MAP (...); BEGIN Process(...); End Process; END Ex1; ARCHITECTURE Ex1 OF Example IS ... END Ex2;
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Library Entity

Architecture

II.1. Library Cc thnh phn (package) ca th vin chun IEEE:

Dng chung vi tt c cc cng c lp trnh. IEEE cng khai m ngun ca th vin ny.

Cc cng c pht trin ca cc hng khc nhau c th c th vin ring.

-- Cc th vin ny c khai bo sn khi to Project LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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II.2. Entity Xc nh: s lng, chiu, kiu cc cng vo/ra v mt s tham s khc.
-- Entity Declaration ENTITY Adder IS GENERIC (iCount : INTEGER); PORT (A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(15 downto 0); S : OUT STD_LOGIC_VECTOR(15 downto 0); C : OUT STD_LOGIC); END Adder;

II.3. Architecture Gia 2 t kha Architecture v Begin l khai bo, lit k cc phn t bn trong ca vi mch, bao gm:
Tn hiu (signal) Thnh phn (component)

Gia 2 t kha Begin v End l on m m t kt ni gia cc thnh phn bn trong v hot ng ca vi mch.

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II.3. Architecture (tip)

-- Architecture Body ARCHITECTURE Adder16 OF Adder IS

signal Cr : STD_LOGIC_VECTOR(16 downto 0);

BEGIN ... PROCESS (...) ... END PROCESS; END Adder16;

Cng 1 Entity ta c th nh ngha nhiu Architecture khc nhau. Tuy nhin, 1 Architecture ch gn vi mt Entity xc nh.
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II.4 Khi nim Process Cc cu lnh nm ngoi Process c thc hin ng thi (concurrent) Cc cu lnh nm trong Process c thc hin tun t (sequential) Process c kch hot khi 1 trong cc tn hiu trong sensitivity list thay i gi tr.
Cc tn hiu trong sensitivity list thng l cc tn hiu u vo ca vi mch.
PROCESS (Clk, Rst,...) ... END PROCESS;
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II.4 Khi nim Process (tip) Nu c nhiu Process th cc Process ny c thc hin ng thi chuyn gi tr t mt process sang mt process khc ta phi dng tn hiu (signal)
P1: Process (Rst) S <= 0000

P3: Process (Clk)

S <= DI and B

P2: Process (S)

S S DO <= S and A
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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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III. Cc i tng trong VHDL Component: Mt thit k VHDL hon chnh c th c chia thnh nhiu thnh phn nh hn. Signal: biu din dy ni, kt ni cc cng ca cc thnh phn vi nhau.
tn hiu ch i gi tr khi kt thc 1 chu k lnh v yu cu v ng b

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III. Cc i tng trong VHDL (tip) Variable: l cc bin c s dng tnh ton, lu cc gi tr trung gian.
bin nhn gi tr ngay khi c gn, gi tr mi ny c th c s dng ngay trong dng lnh tip theo bin ch s dng c trong phm vi Process

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III. Cc i tng trong VHDL (tip)

Clk Clk1 Component_1 Key_In Key_Out Encryptor

Key

Key_1_2
Key_In Plain Data Component_2 Cipher

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III. Cc i tng trong VHDL (tip)

entity architecture component 1 Signals process Input Ports component 2 Variables Output Ports

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III. Cc i tng trong VHDL (tip)

Architecture Example1 of Example is -- Khai bo cc thnh phn Component Component_1 Port ( Clk1: in std_logic; Key_In: in std_logic_vector(1 to 32); Key_Out: out std_logic_vector(1 to 32)); End Component; ... -- Khai bo tn hiu ... -- Khai bo cc kt ni ... -- M t hot ng ... End Example1
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III. Cc i tng trong VHDL (tip)

Architecture Example1 of Example is -- Khai bo cc thnh phn ... -- Khai bo cc tn hiu signal Key_1_2: std_logic_vector(1 to 32); -- Khai bo cc kt ni ... -- M t hot ng ... End Example1 -- C th gn tr mc nh cho tn hiu khi khai bo signal wire: std_logic := 1; signal bus: std_logic_vector(3 downto 0) := 1010;
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III. Cc i tng trong VHDL (tip)

Architecture Example1 of Example is

-- Khai bo cc thnh phn ... -- Khai bo cc tn hiu ... -- Khai bo cc kt ni Com1: Component_1 Port map (Clk => Clk1, Key_In => Key, Key_Out => Key_1_2); -- M t hot ng ...
End Example1
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III. Cc i tng trong VHDL (tip)

Architecture Example1 of Example is -- Khai bo cc thnh phn ... -- Khai bo cc tn hiu ... -- Khai bo cc kt ni ... -- M t hot ng Begin Process (...) variable i: integer range 0 to 15; constant pi: real := 3.14; Begin ... End Process End Example1
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III. Cc i tng trong VHDL (tip) Generic

S dng Generic cho php khai bo cc tham s chung c th s dng mt cch linh hot, mm do trong nhiu tnh hung. Generic l thnh phn khng bt buc trong thit k VHDL.
Entity Example is Generic (iCount: integer; iTime: time); Port (...); End Example;

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III. Cc i tng trong VHDL (tip)

LIBRARY IEEE; Use IEEE.std_logic_1164.ALL; ENTITY Example IS GENERIC (rise, fall: time; load: integer); PORT (inA, inB, inC, inD: In std_logic; out1, out2: Out std_logic); END Example; ARCHITECTURE Ex1 OF Example IS COMPONENT Com1 GENERIC (rise, fall: time:= 10 ns; load: integer:= 0); PORT (a, b: In std_logic; c: Out std_logic); END COMPONENT; BEGIN U1: Com1 GENERIC MAP (10 ns, 12 ns, 3); PORT MAP (inA, inB, out1); U2: Com1 PORT MAP (inC, inD, out2); END Ex1;
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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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IV. Cc kiu d liu bit, bit_vector

thng dng nh ngha bin (variable) ch nhn cc gi tr 0, 1

std_logic, std_logic_vector
thng dng nh ngha tn hiu (signal) nhn cc gi tr: U (Uninitialized), 0, 1, X (Forcing Unknown), Z (High Impedance),

boolean
true, false
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IV. Cc kiu d liu (tip) Integer

32 bit (-2,147,483,647 ... +12,147,483,647) a := 1; a := -1; -- ng a := 1.0; -- sai

Real
32 bit (-10^38 ... +10^38) chnh xc: 7 ch s phn thp phn a := 1; a := -1; -- sai a := 1.0; -- ng a := -1.0E10; a := 1.5E-20; -- ng
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IV. Cc kiu d liu (tip) Kiu d liu t nh ngha

1. Kiu d liu lit k
Thng dng khi m t trng thi

2. Kiu d liu mng 1 chiu

TYPE MyState IS : (Start, S1, S2, S3, Stop); ... variable S : MyState; ... S := S1; TYPE MyRegister IS ARRAY (0 to 255) OF INTEGER; ... variable R : MyRegister; ... R(1) := 1;
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IV. Cc kiu d liu (tip) Kiu d liu t nh ngha

3 Kiu d liu mng nhiu chiu
Thng dng vi chc nng bng tra gi tr (Lookup Table)

TYPE LUT IS ARRAY(0 TO 3, 0 TO 3) OF std_logic; ... constant MyLUT : LUT := ((0, 0, 0), (0, 0, 0), (0, 0, 1));

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IV. Cc kiu d liu (tip) Time

Thi gian l kiu d liu vt l duy nht c nh ngha sn trong VHDL Dng xc nh tr v ng b tn hiu (vi t kha wait) n v: fs, ps, ns, us, ms, sec, min, hr
variable T : time; ... T := 1 ns;

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IV. Cc kiu d liu (tip) C th ni: khng c khi nim p kiu trong VHDL. Mt s ngoi l:
integer +/- bit_vector/std_logic_vector Xt v d:
TYPE long is integer range -100 to 100; TYPE short is integer range -10 to 10; Signal x: short; Signal y: long; ... y <= 2 * x + 5; -- Sai y <= long(2 * x + 5); -- OK -- trong trng hp ny, thc cht x v y -- c cng kiu l integer
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IV. Cc kiu d liu (tip) chuyn i kiu d liu, c 2 cch:

T vit mt on m chuyn d liu. Khai bo th vin v dng hm c sn.

Gi std_logic_arith trong th vin IEEE c mt s hm chuyn i kiu d liu:

conv_integer(p) conv_unsigned(p, b) conv_signed(p, b) conv_std_logic_vector(p, b)
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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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V. Cc php ton Php gn

i vi tn hiu: <=, i vi bin: := kiu v kch thc d liu 2 v ca php gn phi ging nhau

Php ghp vector (concatenation)

dng vi kiu bit_vector/std_logic_vector
signal DI1 : bit_vector (7 downto 0) := 11000110; signal DI2 : bit_vector (3 downto 0) := 0010; signal DO : bit_vector (7 downto 0); DO <= DI1(7 downto 4) & DI2; -- 11000010
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V. Cc php ton (tip) Php ton logic

Ton t: and or not xor nor nand xnor Ton hng: boolean, bit, bit_vector, std_logic, std_logic_vector Cc ton hng vector phi cng kch thc v php ton c thc hin trn cc bit tng ng

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V. Cc php ton (tip) Php ton so snh

Ton t: =, /=, <, <=, >, >= Tr v gi tr boolean (true/false)

Php ton s hc
*, /, ** (exp) ch dng vi integer, real, time. mod, rem ch dng vi integer. +,- dng vi c integer, real, time v bit_vector, std_logic_vector +,- cho php 1 ton hng integer v 1 ton hng bit_vector/std_logic_vector (THB)
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V. Cc php ton (tip) Php ton shift (dch bit)

Ton t: sll, srl, sla, sra, rol, ror Ton hng tri: bit_vector/std_logic_vector Ton hng phi: integer
signal DI : bit_vector (7 downto 0) := 11000110; signal DO : bit_vector (7 downto 0); DO DO DO DO DO <= <= <= <= <= DI DI DI DI DI sll sla srl sra ror 2; 2 2; 2; 3 -----00011000 00011000 00110001 11110001 11011000

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V d 1: (cu hi)
Thit k b cng y (Full Adder) 16bit
Ch : v d ch mang tnh minh ha v php cng C <= A + B c nh ngha sn.
a a b cin b 0 1 cin 0 0 s 0 1 cout 0 0 0 0

Full Adder

s cout

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1 0 0 1

0
1 0 1 0

0
0 1 1 1

1
0 1 0 0

0
1 0 1 1

s <= a xor b xor cin; cout <= (a and b) or (cin and (a xor b));

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V d 1: (tr li)
ENTITY Adder IS PORT (B : IN STD_LOGIC_VECTOR(15 downto 0); A : IN STD_LOGIC_VECTOR(15 downto 0); S : OUT STD_LOGIC_VECTOR(15 downto 0); C : OUT STD_LOGIC); END Adder; ARCHITECTURE Adder16 OF Adder IS signal Cr : STD_LOGIC_VECTOR(16 downto 0); BEGIN PROCESS (A, B) variable i : integer; Begin Cr(0) <= '0'; For i in 0 to 15 loop S(i) <= A(i) xor B(i) xor Cr(i); Cr(i+1) <= (A(i) and B(i)) or (Cr(i) and (A(i) xor B(i))); End loop; C <= Cr(16); END PROCESS; END Adder16;
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V d 2: (cu hi) Xy dng b nhn 2 s 8bit i vi kiu std_logic_vector.

x3 x2 x1 x0 y3 y2 y1 y0

(phn tr li tham kho m ngun km theo)

x3 x2 x1 x0 and y0
x3 x2 x1 x0 x3 x2 x1 x0 x3 x2 x1 x0 z3 z2 z1 z0 z3 z2 z1 z0
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and y1 and y2 and y3

V d 3: (cu hi) Xy dng b chia chia s 16bit cho s 8bit i vi kiu std_logic_vector.

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Bi tp 1: Xy dng b cng 2 s du phy ng

(hc vin t tm hiu s du phy ng)

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Bi tp 2: Xy dng b nhn 2 s du phy ng

(hc vin t tm hiu s du phy ng)

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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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VI. Cc mnh tun t 1. IF 2. CASE 3. LOOP

For ... Loop While ... Loop

4. WAIT
Wait on ... Wait for ... Wait until ...
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VI.1. Mnh IF
IF (biuthclogic1) THEN ... ELSIF (biuthclogic2) THEN - c th c nhiu ELSIF ... ELSE - nhng ch c 1 ELSE ... A END IF; M B U S process (A, B, C, D, Sel ) C X begin D if (Sel = 00) then S <= A; elsif (Sel = 01) then S <= B; elsif (Sel = 10) then S <= C; elsif (Sel = 11) then S <= D; else S <= 0000; end if; end process;
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Sel

VI.2. Mnh CASE

CASE (bin / tnhiu) IS WHEN gitr1 => ... WHEN gitr2 => ... WHEN OTHERS => ... END CASE; process (A, B, C, D, begin case (Sel) is when 00 => S when 01 => S when 10 => S when 11 => S when others => end case; end process; Sel ) A B M U X

C
<= A; <= B; <= C; <= D; S <= 0000; D

Sel

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VI.2. Mnh CASE (tip) Ta c th s dng 1 di gi tr hu hn trong biu thc logic ca mnh CASE hoc IF.
if (x = 12 to 14) then ... end if; case (D_In) is when 1000 to 1010 => ... ... end case;

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VI.2. Mnh CASE (tip) Xt v d

C php hon ton ng. S c th c gn cng lc 1 gi tr A v 3 gi tr 0000. S trong trng hp ny c gi l multi-driver signal. C th tng hp c nhng kt qu sai!
Architecture Bad of MUX is Begin S <= A when Sel = 00 else S <= B when Sel = 01 else S <= C when Sel = 10 else S <= D when Sel = 11 else End Bad;
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0000; 0000; 0000; 0000;

VI.2. Mnh CASE (tip)

Kt qu sai l do hin tng chp mch (short-circuit) khi tng hp. Thc t c rt nhiu tn hiu nhn gi tr t nhiu ngun (source) khc nhau (ngun tn hiu ca S l A, B, C, D).

Cch x l
Ngi thit k/lp trnh phi phn gii gi tr t nhiu ngun khc nhau tn hiu ch nhn 1 gi tr duy nht ti 1 thi im (multisource - single-driver).

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VI.3. Mnh LOOP

PROCESS (A_Sig, B_Bus) variable i : integer; Begin for i in 7 downto 0 loop C_Bus(i) <= A_Sig and B_Bus(i); end loop; END PROCESS;

PROCESS (A_Sig, B_Bus) variable i : integer; Begin i := 7; while (i >= 0) loop C_Bus(i) <= A_Sig and B_Bus(i); i := i 1; end loop; END PROCESS;
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VI.3. Mnh LOOP (tip) Dng vng lp ang thc hin d chuyn sang vng lp tip theo: NEXT. Dng vng lp ang thc hin d v thot hn khi vng lp: EXIT.
C th c nhiu vng lp lng nhau, nhng lnh Exit ch c tc dng i vi vng lp trc tip cha n.

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VI.4. Mnh WAIT Mnh WAIT dng tm dng Process trong mt khong thi gian no :
Wait on tn_hiu_no__thay_i_gi_tr Wait until biu_thc_logic_nhn_gi_tr_true Wait for khong_thi_gian_xc_nh Wait (khong_thi_gian_khng_xc_nh)

Wait on A, B; ... Wait until Clk = 1; ... Wait for 10 ns; ... Wait;
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VI.4. Mnh WAIT (tip) Khng phi tt c cc mnh VHDL u c th tng hp c.

V d, wait for 10 ns l mt mnh thng dng trong m hnh ho, nhng n khng tng ng vi v cng khng th to ra mt phn t mc cng logic.

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VI.4. Mnh WAIT (tip) Mnh Wait c th c vit di dng tng minh (explicit) hoc khng tng minh (implicit). Mt s cng c tng hp mch khng h tr explicit wait.
-- Implicit WAIT Process (A, B) Begin C <= A and B; End Process; -- Explicit WAIT Process Begin Wait on A, B; C <= A and B; End Process;

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V d 4: (cu hi) Xy dng h dy on nhn xu 1101

0
A 0 1 1 1 0 1 1

Input Output

(phn tr li tham kho m ngun km theo)

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Bi tp

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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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VII. M ha DES vi VHDL DES = Data Encryption Standard L thut ton m ha khi, lm vic vi khi d liu 64bit. Kha m ha 64bit (thc t ch c 56bit v 8bit cn li dng kim tra) V kha khng di, DES c ci tin thnh Triple_DES (thc hin DES 3 ln vi 3 kha)

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VIII. M ha DES vi VHDL (tip)

...

IP

16 rounds

FP

...

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VIII. M ha DES vi VHDL (tip)

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VIII. M ha DES vi VHDL (tip)

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Ni dung
1 2 3 4 5 6 7 Gii thiu VHDL Cu trc lp trnh Cc i tng Cc kiu d liu Cc php ton Cc mnh tun t DES vi VHDL AES vi VHDL
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VIII. M ha AES vi VHDL AES = Advanced Encryption Standard L thut ton m ha khi, lm vic vi khi d liu 128bit. Kha m ha c th 128, 192 hoc 256bit c chnh ph Hoa K chnh thc s dng thay th Triple_DES.

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VIII. M ha AES vi VHDL (tip)

Plaintext

AddRoundKey CipherKey

SubBytes ShiftRows

MixColumn
SubBytes ShiftRows Ciphertext AddRoundKey RoundKey 10 AddRoundKey RoundKey 1-9

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VIII. M ha AES vi VHDL (tip)

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VIII. M ha AES vi VHDL (tip)

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VIII. M ha AES vi VHDL (tip)

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VIII. M ha AES vi VHDL (tip)

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So snh vi Embedded C Vi x l, vi iu khin c sn tp lnh nn c th dng Embedded C lp trnh, cc lnh C s c dch sang ngn ng my dng nh phn. FPGA ch bao gm cc phn t Logic c bn nn phi s dng VHDL m phng v tng hp di dng ghp ni cc phn t logic. Lm vic vi VHDL i hi hiu su hn v cu trc v hot ng ca vi mch.
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So snh vi Verilog Ging nhau:

Cng l ngn ng m phng v tng hp phn cng. C th so snh nh C++ v Java.

Khc nhau:
VHDL yu cu cu trc cht ch hn (c bit v kiu d liu) nn d pht hin li hn, tuy nhin li thng di dng hn v kh phn tch m ngun hn. VHDL c dng nhiu Chu u, Verilog c dng nhiu M (mc d c 2 u sinh ra M)
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Ti liu tham kho VHDL Programming by Examples, Douglas L.Perry, McGraw Hill. Circuit Design with VHDL, Volnei A.Pedroni, MIT Press. 1076 IEEE Standard VHDL Reference Manual, IEEE Computer Society.

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