UNIT 3:

INTRODUCTION TO VERILOG
VERILOG FOR COMBINATIONAL
CIRCUITS
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY
INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER
(ICDREC)
SEP 09 - 2007

DEPUTY DIRECTOR
Multiplexer the conditional operator
(1 of 4)
A multiplexer circuit has a number of data inputs, one or more
select inputs, and one output. It passes the signal value on one
of the data inputs to the output. The data input is selected by
the values of the select inputs.
The above figures show a 2-to-1 multiplexer. The select input
s, chooses as the output of the multiplexer either input x or y.
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Multiplexer the conditional operator
(2 of 4)
Rather than using gates or logic expressions, we will specify
the 2-to-1 multiplexer in terms of their behavior..
For simple implementation of such multiplexer, Verilog
provides a conditional operator (?) which assign one of
two values depending on a conditional expression.
The syntax of conditional expression:
conditional_expression ? true_expression: false_expression
For example: A = (B < C) ? (D + 5) : (D + 2);
means that if B < C, the value A will be D + 5 or else A will
have the value D + 2.
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Multiplexer the conditional operator
(3 of 4)
Example 1:
Create a Verilog module for the 2-to-1 multiplexer. Connect x
input to SW0, y input to SW1, s select input to SW2, and the
output to LEDG0. Using the conditional operator in
continuos assignment statement.
The conditional operator can be used both in continuous
assignment statements and in procedural statements inside
an always block.
Example 2:
Rewrite the Verilog code in example 1 . Using the
conditional operator in procedural statements
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Multiplexer the conditional operator
(4 of 4)
Example 3:
Create a Verilog module for the
4-to-1 multiplexer by nesting
the conditonal operators.
Connect two its select inputs
s0, s1 to the switches SW4,
SW5. Connect four data inputs
x, y, z and w to SW0 3.
Connect the output signal to
green lights LEDG0.
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Multiplexer the if else statement (1
of 2)
We have already used the if-else statement in unit 2. It has the
syntax:
if (conditional_expression) statement1;
else statement2;
If the conditional_expression is evaluated to true then the first
statement (or a block of statements delineated by begin and
end keywords) is executed or else the second statement (or a
block of statements) is executed.
Example 4:
Rewrite the Verilog code for multiplexer 2-to-1 using the if-
else statement.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Multiplexer the if else statement (2
of 2)
The general form of if-else statement is given as follows.
if (conditional_expression1) statement1;
else if (conditional_expression2) statement2;
else if (conditional_expression3) statement3;

else statementn;
Example 5:
Rewrite the Verilog code for multiplexer 4-to-1 using the if-
else statement.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Multiplexer the case statement
The general form of case statement as follows:
case (expression)
alternative1: statement1;

alternativen: statementn;
[default: statement;]
endcase
Example 6:
Rewrite the Verilog code for multiplexer 4-to-1 using the case
statement.
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Decoder
Example 7:
Write the Verilog code for decoder 2-to-4 using the case
statement. The data inputs are the two-bit vector W, and the
enable input is En. The four outputs are represented by the
four-bit vector Y. Connect W, En to SW1-0 and SW2. Connect
Y to LEDG3-0.
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BCD to 7 segment decoder
Example 8:
Write the Verilog code for
a BCD to 7 segment
decoder , using the case
statement. Connect the
outputs of the decoder to
HEX0 display on the DE2
board.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Priority encoder the casex statement
Example 9:
Write the Verilog code for a priority encoder 4-to-2 using the
casex statement. The data inputs are the four-bit vector W. The
two outputs are represented by the two-bit vector Y. An output
z is provided to indicate the condition which none of the
inputs is equal to 1.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Decoder the for loop
Example 10:
Rewrite the Verilog code for decoder 2-to-4 using the for
loop. Connect W, En to SW1-0 and SW2. Connect Y to
LEDG3-0.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
The for loop has the syntax:
for (initial_index; terminal_index; increment) statement;
A loop control variable,
which has to be of type
integer, is set to the value
given as the initial index.
After each iteration, the
control variable is changed
as defined in the increment.
Priority encoder the for loop
Example 11:
Rewrite the Verilog code for a priority encoder 4-to-2 using
the for loop. The data inputs ,W, are connected to SW3-0. The
two outputs, Y, are connected to LEDG1-0. Connect the output
z to LEDG2
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A case study : multiplexer 8-to-1
(1 of 2)
Example 12:
Write the Verilog code for a multiplexer 8-to-1 using the
conditional opeartor. The data inputs are the eight bits vector
W, are connected to SW7-0. The select inputs are three bits
vector, S, are connected to SW10-8. Connect the output y to
LEDG0.
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG
Example 13:
Write the Verilog code for a multiplexer 8-to-1 using the case
statement. The data inputs are the eight bits vector W, are
connected to SW7-0. The select inputs are three bits vector, S,
are connected to SW10-8. Connect the output y to LEDG0.
A case study : multiplexer 8-to-1
(2 of 2)
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Example 14:
Rewrite the Verilog code
for a multiplexer 8-to-1
using the subcircuits as
multiplexer 4-to-1 and
multiplexer 2-to-1.
Verilog task
A task is declared by the keyword task and it comprises a
block of statements that ends with the keyword endtask.
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Example 15:
Rewrite the Verilog code for a multiplexer 8-to-1 using the
task .
The task must be included in the module that calls it.
The task may have input and output ports. These are not the
ports of the module that contains the task, which are used to
make external connections to the module. The task ports are
used only to pass values between the module and the task.
The output of a task must be a variable.
Verilog function
A function is declared by the keyword function and it
comprises a block of statements that ends with the keyword
endfunction.
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Example 16: Rewrite the Verilog code for a multiplexer 8-to-1
using the function .
The purpose of a function is to allow the code to be written
in a modular fashion without defining separate modules. A
function is defined within a module, and it is called either in
a continuous assignment statement or in a procedural
assignment inside that module.
The function must have at least one input , but it does not have
an output, and it returns a single value (with function name
itseft) that is placed where the function is invoked.