Single Event Upsets in Digital VLSI

Circuits
EYES Summer Internship Program 2007
University of New Mexico

Vinay Jain Dr. Payman Zarkesh-Ha
Final Year Undergraduate Assistant Professor ECE
Indian Institute of Technology Kanpur University of New Mexico

Acknowledgements
Outline
Introduction
Soft-Spot Analysis
Inverter Model proposed
Simulation Results
Extension of the Model
Introduction
Origin
Soft errors, Single Event Transients (SET)
and Single Event Upsets (SEU)
Techniques to reduce SET propagation
Softness of a node
Particle Strike in CMOS Digital VLSI circuits. SET and SEU
Origin of Soft errors: cosmic
neutrons and - particles
Soft-Spot Analysis
Timing Masking Factor, T
N

Tendency of a node to allow noise in particular
time window
Computed using time delays and sensitive
window durations of various gates in the path
Logic Masking Factor, L
N

Likelihood for noise at a node to logically reach
the storage element
Computed using probability of nodes in the path
to acquire certain states
Electrical Masking Factor, E
N
Ability of a node to allow noise propagation
with enough strength
Computed from the characteristics of Noise
Rejection Curves

Overall Softness, S
N
S
N
= T
N
*L
N
*E
N

Noise Rejection Curves
Noise Rejection Curves for an inverter and
its effects as Load and Size of the inverter is varied
Inverter Model Proposed
Model proposed is- replacement of MOS transistors with constant current
sources the DC value of which is the average drain currents of the transistors
A. Velocity Saturation Effects in short channel MOSFETs
= .E / (1 + E / E
C
) , E < E
C

=
SAT
, E > E
C

where E
C
= 2
SAT
/
V
DSATn
= V
GTn
/ (1 + V
GTn
/ E
Cn.
L
n
)
for short channel (small L
n
)
saturates to V
DSATn
= E
Cn.
L
n

as V
GTn
is increased

= V
GTn
, long channel (large L
n
)

I
DSATn
=
SATn
.C
ox
.W
n
.( V
GTn
-V
DSATn
)
=
SATn
.C
ox
.W
n
.(V
GTn
)
2
/ (V
GTn
+ E
Cn.
L
n
)
~
SATn
. C
ox
.W
n
.(V
GTn
) for small channel MOSFETs (small L
n
)
~
SATn
. C
ox
.W
n
.(V
GTn
)
2
/ E
Cn.
L
n
for long channel MOSFETs (large L
n
)
B. Voltage Transfer Characteristic
Voltage Transfer Characteristic for an Inverter
(INVx1)
Noise can propagate only when input pulse has
magnitude greater than V
m
C. Average Current Model
I
D
V
DS
characteristic for an
inverter (INVx1) for gate
Voltage greater than V
m

I
N
=(I
Dn
)
avg
= I
DSATn
(1 +
n
(V
DD
+ V
m
)/ 2)
I
N
= C
n
*. I
DSATn
where C
n
* = 1 +
n
(V
DD
+ V
m
)/ 2

I
P
= (I
Dp
)
avg
= [ (I
P1
/2).<V
DSATp
> + {(I
P1
+I
P2
)/2}.(V
DD
V
m
<V
DSATp
>) ] /
(V
DD
V
m
)
= I
DSATp
.(1 +
p
(V
DD
- V
m
)/ 2 <V
DSATp
>/(2.(V
DD
- V
m
)) )
Thus,
I
P
= C
p
*. I
DSATp

where C
p
* = 1 +
p
(V
DD
- V
m
)/ 2 <V
DSATp
>/(2.(V
DD
- V
m
))

<V
DSATp
> = V
DSATp

at V
G
= (V
DD
+ V
m
)/ 2

I
P1
= I
DSATp
. (1+
p
.<V
DSATp
>)
I
P2
= I
DSATp
. (1+
p
.(V
DD
- V
m
))
Thus, we have I
N
= C
n
*I
DSATn

& I
P
= C
p
*I
DSATp

where both C
n
* & C
p
* are constants and close to unity.
We can now calculate T
C
as the minimum duration
required for a noise pulse of height V
C
volts, to
propagate through the inverter as

T
C
= C
L
.(V
DD
- V
m
)/(I
N
- I
P
)
with V
G
= V
C


The above equation gives a relation between T
C
and V
C

as a function of only Gate size (W and L) of p-MOS
and n-MOS.
Simulation Results
Noise Rejection Curves comparison for INVx2
(Load = 200fF)
Time taken for simulation by matlab = 0.077 sec
Time taken for simulation by Tspice = 4.45 sec
Mean %error = 4.68%
Noise Rejection Curves comparison for INVx1
(Load = 200fF)
Time taken for simulation by matlab = 0.074 sec
Time taken for simulation by Tspice = 4.48 sec
Mean %error = 11.59%
Noise Rejection Curves comparison for INVx8
(Load = 200fF)
Time taken for simulation by matlab = 0.069 sec
Time taken for simulation by Tspice = 4.42 sec
Mean %error = 17.65%
Noise Rejection Curves comparison for INVx4
(Load = 200fF)
Time taken for simulation by matlab = 0.074 sec
Time taken for simulation by Tspice = 4.61 sec
Mean %error = 6.70%
Extension of the model
Modeling of NAND gates for easy computation of Noise Rejection Curves
Modeling of NOR gates for easy computation of Noise Rejection Curves
Noise Rejection Curves comparison for
NANDx1 (Load = 200fF)
Time taken for simulation by matlab = 0.078 sec
Time taken for simulation by Tspice = 5.05 sec
Mean %error = 30.16%
Noise Rejection Curves comparison for
NORx1 (Load = 200fF)
Time taken for simulation by matlab = 0.076 sec
Time taken for simulation by Tspice = 5.09 sec
Mean %error = 9.23%
References
[1] C. Zhao, X. Bai, S. Dey, A scalable soft spot analysis methodology for
compound noise effects in nano-meter circuits, DAC04, pp. 894-899, June
2004.

[2] C. Zhao, S. Dey, Improving transient error tolerance of digital VLSI circuits
using RObustness COmpiler (ROCO), International Symposium on Quality
Electronic Design, ISQED06

[3] C.G. Sodini, P. Ko, J. Moll, The effect of high fields on MOS device and circuit
performance, IEEE transactions on Electron Devices, October 1984, pp.1386-
1393

[4] J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits,
Second edition, 2003

Thank You