STATIC

TIMING
ANALYSIS
Nitish Agarwal
070907542

Place Of Internship

SoC Players

SoC
Flow

STA is a method of validating the

timing performance of a design by
checking all possible paths for
timing violations.
It is much faster than dynamic
simulation because it is not
necessary to simulate the logical
operation of the design

Timing Need ?
15%
delay
85%
delay

50%
delay

Mid 80 Scenario
Most of the input to output
delay of the logic is due to
gate delay

Mid 90 Scenario
Half of input to output delay of
the logic is due to wire delay

50%
delay

Todays Scenario
80%
delay
20%
delay

Most of input to output delay

of the logic is due to wire
delay

STA Advantage
Speed (orders of magnitude faster
than dynamic simulation)
Capacity to handling full chip
Exhaustive timing coverage
Test vectors are not required

STA disadvantage
It is pessimistic (too conservative)
Reports false paths

Static Timing Analysis v/s Dynamic

Timing Analysis
Static analysis is performed by
calculating all possible delays
between points of connectivity in a
circuit.
Dynamic analysis is only performed
on nets that are stimulated by
applying vectors to a simulation
model.

Flow Inputs
Gate-level Netlist
Constraints (SDC Standard Design
Constraint)
Extracted nets (SPEF Standard
Parasitic Exchange Format)
Libraries (liberty format - .lib)

Flow Output
Standard Delay Format (SDF)

STA INTERACTION
Synthesis Team

APR Team
.v & .spef

constraints

constraints

SIGNOFF

STA Team

Modes understanding

Team DFT

Modes understanding

SDF

FE Team

Timing Iterations
SYNTHESIS
Timing Met ?
PLACEMENT

Constraints

Timing Met ?

Timing Analysis
and Fixes

Timing Analysis
and Fixes

CTS / Routing
Timing Met ?
NOISE

Timing Analysis
and Fixes

Maturity Of Design
PreCTS

Uncertainty = Skew + Jitter + Tool margin + Ocv margin

+ Delay noise margin

Post CTS

Uncertainty = Jitter + Tool margin + Ocv margin + Delay

noise margin

After OCV stage

Uncertainty = Jitter + Tool margin + Delay noise margin

Noise Analysis

Uncertainty = Jitter + Tool margin

Analysis modes
Single operating condition
Min-Max (BC-WC) operating condition
On-chip-variation mode

Single operating condition

Single set of delay parameters is
used for the
whole circuit, based on one set of
process, temperature, and voltage
conditions.

Min-Max (BC-WC) operating

condition
Simultaneously checks the circuit for
the two extreme operating
conditions, minimum and maximum.
For setup checks, it uses maximum
delays for all paths. For hold checks,
it uses
minimum delays.

On-chip-variation mode
Conservative analysis that allows both
minimum and maximum delays to apply to
different paths at the same time.
For a setup check, it uses maximum delays
for the launch clock path and data path, and
minimum delays for the capture clock path.
For a hold check, it uses minimum delays for
the launch clock path and data path, and
maximum delays for the capture clock path.

Path Types

Checks

Constraints Check
CONSTRAINT
S
Clock Definition

Primary clocks
Generated clocks
Latency
Uncertainty

Exceptions

Multi cycle paths

False paths
Case Analysis
Disable timing
Set Max/Min Delay

IO Constraints
Input delays
Output delays
DRC Constraints

STA RUN CYCLE

Read the design data (A gate level
netlist and associated technology
.lib)
lu_table_template(table_1){

index_1(" 0.011, 0.04035, 0.0807, 0.1614, 0.3228, 0.6456, 1.2912, 2.69 ");
index_2(" 0.0027, 0.004306, 0.005912, 0.009124, 0.015548, 0.028396, 0.054092,
0.083 ");
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
}
cell_fall(table_1){
values("0.231350, 0.244700, 0.256620, 0.277960, 0.315520, 0.382970,
0.509850, 0.650100",\
"0.253300, 0.266640, 0.278570, 0.299930, 0.337500, 0.404960,
0.531860, 0.672070",\
"0.283930, 0.297270, 0.309190, 0.330560, 0.368200, 0.435680,
0.562560, 0.702930",\
"0.342790, 0.356240, 0.368270, 0.389790, 0.427610, 0.495260,
0.622250, 0.762640",\
"0.448280, 0.462200, 0.474570, 0.496590, 0.535030, 0.603280,
0.730630, 0.870880",\

 Constrain the design by specifying the

clock characteristics, input timing
conditions and output timing requirements.
Specify environment and analysis
conditions such as operating conditions,
case analysis settings, net delay modes
and timing exceptions.
Check the design data and analysis
setup(scripts) parameters for a full timing
analysis.
Perform a full timing analysis and analyse
the results.

Correlation
Table

Chip Size Reduction

Decreasing Size Effect

Some minor advances in STA have
been made such as the use of
composite current models (CCS)
models and distributed multimode/multi-corner (MM/MC) and
location-based on-chip variation
(LOCV) analysis.

How many minimum modes i should qualify STA for a chip

1. Scan Shift mode
2. Scan Capture mode
3. MBIST mode
4. Functional modes for Each Interface
5. Boundary scan mode
6. scan-compression mode
How many minimum process lots , should STA be qualified.
1. Fast corner
2. Slow corner
3. Typical corner
How many minimum Timing , Should STA be qualified.
1. normal delay mode(with out applying deration)
2. On-chip variation mode ( deration applied)
3. SI mode (Signal integrity cross talk impact on STA)
How many minimum STA runs should we needed to address = 6*3*3.