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UNIT-V
Multiplier
11
24
R2
44
2
3
Clr
;Clear Accumulator A
Rep
MAC
*(R0)+, *(R1)+, A
Mov
A, *R2
Harvard architecture
Memory
Register 1
ALU
Register 2
Data
Memory
A DSP Chip is a
microprocessor specially
designed for DSP
applications
Harvard architecture allows
multiple memory reads
Architecture optimized to
provide rapid processing of
discrete time signals, e.g.
Multiply and Accumulate
(MAC) in one cycle
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Multiplexe
r
Multiplexe
r
ALU
Accumulator
Memory structures
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PIPELINING :
Pipelining is a technique which follows two or more operations to
overlap during execution.
In pipelining, a task is broken down into a number of distinct
subtasks which are then overlapped during execution. It is used
extensively in digital signal processors to increase speed.
An instruction can be broken down into three steps. Each step in
the instruction can be regarded as a stage in a pipeline and so can
be overlapped. By overlapping the instructions , a new instruction is
started at the start of each clock cycle.
The figure shows the timing diagram for a three-stage pipeline ,
drawn to highlight the instruction steps. Typically , each step in the
pipeline takes one machine cycle. Thus, during a given cycle up to
three diferent instructions may be active at the same time ,
although each will be at the diferent stage of completion.
The key to an instruction pipeline is that three parts of the
instruction (that is fetch, decode and execute) are independent and
so the execution of multiple instructions can be overlapped.
It is seen that at the ith cycle , the processor could be
simultaneously fetching the ith instruction , decoding the (i-1)th
Types of DSP
Low End Fixed Point
TMS320C2XX, ADSP21XX, DSP56XXX
Floating Point
TMS320C3X, C67XX, ADSP210XX, DSP96000,
DSP32XX
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Figure 3.3 (a) An A/D converter with b bits for signal representation,
(b) quantization model for the A/D converter
Figure 3.4 An example showing the D/A converter error due to the
zero-order hold at its output: (a) DSP output, (b) D/A output,
Figure 3.4 An example showing the D/A converter error due to the
zero-order hold at its output: (c) the convolving pulse that generates
(b) from (a), (d) frequency contents of the convolving pulse in (c)
cheaper
smaller
less power consuming
Harder to program
Watch for errors: truncation, overflow, rounding
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Fixed Point
Applications
Applications
Modems
Portable Products
Wireless Basestations
Electronic Books
Digital Imaging
Voice Recognition
3D Graphics
GPS Receivers
Speech Recognition
Headsets
Voice over IP
Biometrics
Fingerprint Recognition
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