Chapter 4 (Stallings)

Main (Internal)
Memory

Memory : Place of Programs and Data

3.1. Computer Components :
CPU
IR
PC

Memory

MAR
MBR

...

Instruction

Instruction
Instruction

R1

R3

R2

R4

...
Data
I/O Module

Data
Data
n

Buffers

Memory Hierarchy - Diagram

4.1 Computer Memory System

Overview

Key Characteristic of Computer Memory System

Location
CPU
Internal(main)
External (secondary)
Capacity
Word size
Number of words
Unit of Transfer
Characteristics
Word
Block
Access Method
Sequential access
Direct access
Random access
Associative access

Performance
Access Time
Cycle time
Transfer rate
Physical Type
Semiconductor
Magnetic surface
Physical
Volatile/nonvolatile
Erasable/non erasable
Organization

Memory Hierarchy

Characteristics - continued
Capacity is expressed in terms of bytes or words
Word : the : natural unit of organization of
memory. Cray-1 has 64 bit while VAX machines
have 32 bit word
Addressable Units : If address is A bits then
amount of addressable units (maximum) is 2 A
Unit of Transfer : number of bits read-out of
memory or written into memory
Methods of access :
Sequential, Direct, Random and Associative

Characteristics - continued
Performance Measures :
Access Time : for random access memory
(RAM), this is time it takes to perform a read or
write operation; that is, time from the address is
presented to memory to the instant that data or
instruction have been stored or made available
Memory Cycle Time : concept applies to RAM,
is the access time (of a unit of information) and
any additional time needed for transient, before
the second access can commence.
Transfer Rate : time needed for the data to be
transferred into or out of a memory unit. For
RAM, it is equal to 1/(Cycle Time).

Characteristics

performance continued

There are other physical characteristics

such as :
Volatile or non volatile, destructive
read out, Read Only Memory, etc.

Memory Hierarchy

For most memory technology, the following

rules hold :
- Smaller access time, greater cost per bit
- Greater capacity, smaller cost per bit
- Greater capacity, greater access time
Memory hierarchy, as goes down the hierarchy
:
a. Decreasing cost per bit
b. Increasing capacity
c. Increasing access time
d. Decreasing frequency of access by CPU

Semiconductor Memory
RAM
Misnamed as all semiconductor
memory is random access
Read/Write
Volatile
Temporary storage
Static or dynamic

Memory Cell Operation

Basic Organization

j1

i1

i2

j2

Dynamic RAM

Bits stored as charge in capacitors

Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
Level of charge determines value

Dynamic RAM Structure

DRAM Operation
Address line active when bit read or written
Transistor switch closed (current flows)

Write
Voltage to bit line
High for 1 low for 0

Then signal address line

Transfers charge to capacitor

Read
Address line selected
transistor turns on

Charge from capacitor fed via bit line to sense

amplifier
Compares with reference value to determine 0 or 1

Capacitor charge must be restored

DRAM Strength and Weaknesses

Strength
Single active component (transistor)
makes this type of memory relatively
cheap
Each transistor holds one bit
v
Weaknesses
Charges leak from capacitor
voltage drop gradually
needs refresh

Static RAM

Bits stored as on/off switches

No charges to leak
No refreshing needed when powered
Does not need refresh circuits
More complex construction
Larger per bit
More expensive
Faster
Cache
Digital
Uses flip-flops

Static RAM Structure

Static RAM Operation

Transistor arrangement gives stable logic
state
State 1
C1 high, C2 low
T1 T4 off, T2 T3 on

State 0
C2 high, C1 low
T2 T3 off, T1 T4 on

Address line transistors T5 T6 is switch

Write apply value to B & compliment to B
Read value is on line B

SRAM v DRAM
Both volatile
Power needed to preserve data

Dynamic cell
Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units

Static
Faster
Cache

Read Only Memory (ROM)

Permanent storage
Nonvolatile

Microprogramming
Library subroutines
Systems programs (BIOS)
Function tables

Other memories :
Flash memory (due to its fast reprogrammability)
RAMBUS (manufactured by RAMBUS)

Organisation in detail
A 16Mbit chip can be organised as 1M of
16 bit words
A bit per chip system has 16 lots of 1Mbit
chip with bit 1 of each word in chip 1 and
so on
A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4
capacity

Refreshing

Refresh circuit included on chip

Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance

Typical 16 Mb DRAM (4M x 4)

Module
Organisation

Module Organisation (2)