IMPLEMENTATION OF FLOATING

POINT SUBTRACTION AND

DIVISION
PROJECT GUIDE
PROJECT MEMBERS
A. Kiran Kumar
Raviteja

P
13004037
N

Rohith

13004039
A Sai

Raj Venkat

13004057

FLOATING POINT
REPRESENTATION
In computing, floating point is the formulaic representation that
approximates a real number so as to support a trade-off between range
and precision.
For example in base 10 format 0.125 is represented as

0.125=1.25 x 10-1

FLOATING POINT
REPRESENTATION
Numbers written in scientific notation have three components
Sign Bit 1-bit
Mantessa 23- bit
Exponent 8-bit
Sign

Exponent

Significand

Significand is the term reffered to the fractional part of the floating

point number.

FLOATING POINT
REPRESENTATION
The one-bit sign field is the sign of the stored

value.
The size of the exponent field determines the
range of values that can be represented.
The size of the significand determines the
precision of the representation.
So 4.5 in binary format is 100.1
This should be normalized according to IEEE rule
After normalization
1.001 x 22
biasing
factor is 127
0
10000001
00100000000000000000000
127+2=129
hence the floating
point
representation is

FLOATING POINT ARITHMETIC OPERATIONS

The steps to be considered For floating point
arithmetic operations
Step 1: Perform arithmetic
operations
mantessa of the both operands.
Step 2: Adjust the decimal point with respect to
Exponent.
Step 3: Bias the both exponents and add them.
Step 4: obtain the resultant sign by the
operation on sign bits of both operands.
Step 5: Round the resulting data so as to fit
required bits, that is 23 bit.

on
the

xor
the

BLOCK DIAGRAM

FLOATING POINT
SUBTRACTION
First the given two real numbers are converted into floating

point format.
The subtraction operation is performed based on the
following formula
X-Y = (Mx My x 2Ey - Ex ) x 2Ex
X & Y are the floating point representations of
given real numbers.
Mx & My are the mantessa of the operands X & Y
Respectively.
Ex & Ey are the exponents of X & Y Respectively.

FLOATING POINT DIVISION

First the given two real numbers are converted into floating

point format.
The Division operation is performed based on the following
formula.
X/Y = (Mx/My) x 2Ex-Ey
Also X/Y = X*(1/Y)= (Mx*My) x 2Ex-Ey
X & Y are the floating point representations of given
real numbers.
Mx & My are the mantessa of the operands X & 1/Y
Respectively.
Ex & Ey are the exponents of X & 1/Y Respectively.

FLOATING POINT ACCURACY

Three factors influence the greater accuracy inherent in the

floating-point format.
First, the 24-bit I/O word width of floating-point DSPs yields
greater precision, in integer as well as real values, than the 16bit word width that is common in fixed-point devices.
Second, exponentiation vastly increases the dynamic range
available for the application. A wide dynamic range is
important in dealing with extremely large data sets and with
data sets where the range cannot be easily predicted.
Third, the internal representations of data in floating-point
hardware are more exact than in fixed-point, ensuring greater
accuracy in end results.

IMPLEMENTATION
Verilog is the Hardware descriptive language for

designing the hardware for our desired system

based on coding. It is commonly used for
desigining and verification of the digital devices
at register transfer level.
There are three types of Verilog Design Styles
Data Flow Modeling .
Behavioural Modeling or Algorithm level modeling
Gate level Modeling or Structural Modeling

IMPLEMENTATION
Data flow level: this is implemented by specifying the data

flow, I.e registers used in the design.

Behavioural level: this is highest level of abstraction. It is

implemented with design algorithms. Here the designer

necessarily not need to know the exact hardware implemtation
knowledge.
Gate level: this is implemented using logic gates. The designer

here must know the exact gate level diagram of the design.

REFERENCES
http://

rtcmagazine.com/articles/view/100255
https://www.doc.ic.ac.uk/~eedwards/compsy

s/float
/