ECE-E434 Digital Electronics

Lectures 18: VLSI Fabrication Process

Instructor: Pouya Dianat
Nov 21 2017
 Announcements
• Term project is uploaded on Bblearn.
• Special Assignment is uploaded.
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

General steps on VLSI fabrication

• Silicon Wafer: Watch this  https://youtu.be/XbBc4ByimY8
• Oxidation:
• Thermally grown SiO2 with excellent insulation properties;
• Requires high temperatures
• Photolithography: To transfer patterns to the substrate
• Etching: Wet vs Dry; Isotropic vs anisotropic
• Intentional impurity incorporation:
• Diffusion: Easy; High temperature; Inaccurate profile
• Ion Implantation: Room temperature; Accurate Profile; Destructive
• Device Layer Depositions:
• Chemical Vapor Deposition:
• Chemical process for Si3N4, SiO2, Polysilicon
• Fast; Low temperature; Not a high quality material
• Metallization
• Packaging:
• Testing: Performed while the chips are on the wafer
• Dicing: Chips are cut from the wafer into dies
• Mounting: Each die is mounted in its on package
Let’s watch this: https://youtu.be/Q5paWn7bFg4
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

What is photolithography?
• In photolithography, desired patterns, as designed on a mask, are transferred to a silicon
wafer.
• UV light is shone through the mask on a wafer with a film of photo-sensitive polymer aka
photoresist.
• Depending on type of the photoresist, the exposed regions either stay or removed
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Photolithography

• In a typical process, different masks are used

at different steps of the process, e.g.:
• A specific mask for Ion Implantation
• Another mask for etching
• A different mask for metallization
• …
• >20 different masks are used for for typical
VLSI
• It requires precise alignment at each stage.
Remember transistor sizes?
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Twin-well CMOS Process Steps

• An n-well is made through ion

implantation of P dopants

• Shallow Trench Isolation to define

active region of devices.
• Device boundaries are (dry) etched
300nm deep.
• The trenches are filled with CVD oxide
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Twin-well CMOS Process Steps

• Polysilicon gates are deposited
• First, native oxide is removed
• A high quality thin oxide is grown
(2-5nm)
• A polysilicon is deposited and
patterned

• The polysilicon gate is then doped by

Ion Implantation.
• Lightly doped regions are formed on
source and drain.
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Twin-well CMOS Process Steps

• Silicon Nitride is deposited and
patterned to protect the LLD regions
• These regions prevent formation of hot
electrons.

• p+ and n+ regions are formed for

source and drain through ion
implantation
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Twin-well CMOS Process Steps

• A thick CVD oxide is deposited and
patterned to define contact holes

• Metallization is performed to make

electrical contact to the device nodes.
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Circuit elements in VLSI: Resistors

• Resistors are typically made through diffusion method for making n, n+, or p+
• Their tolerance value is really poor (%20-50), however:
• Different resistors may be matched with a great tolerance (%5)
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Circuit elements in VLSI: Capacitors

• Capacitors can be made with only %1 error.
• They can be matched with %0.1 accuracy.
 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Other devices is MOS technology

 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Layout for a typical CMOS inverter

 ECE-E434
Digital Electronics
VLSI Fabrication – Appendix A

Masks need to be generated from Layout