Library, Components and

Configurations
Dr. Yann-Hang Lee
yhlee@asu.edu
Design Hierarchy

 A design consists of multiple entities (design units)

 could be declaration or architecture units
 After analysis, store the units in a design library
(consists of design units)
 Group a collection of related objects (declaration and
body) into a package
 as a design unit
 To invoke a design unit:
 library name  where it is (physical file)
 which design unit

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LIBRARY Statements

 Purpose: design partition and reuse

 To invoke design units (libraries) –
library logical_name(s) ;
 A means is needed to explicitly describe where
designs are to be found --
 either to import declarations, or
 to select between collections of entities and
architectures.

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LIBRARY Statements

 Within a VHDL description one may specify LOGICAL library

names, which then can be used as part of an extended naming
scheme.
 The logical name can then be associated with a file name at the
system level when the tool is invoked.

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USE Statements

 explicitly provides a naming "scope," somewhat like the "WITH"

statement in Pascal.
 Forms:

 library_name.package_name.ALL
even if the library_name is WORK
 package_name.object -
requires that the package be defined in the same file
 library_name.package_name.object

 Examples:
library ASIC;
use ASIC.gate_array.all;

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Special Library: STD

 explicitly prescribed by VHDL:

 whose contents are predefined by the VHDL language,
containing:
 package STANDARD
with type declarations for bit, bit_vector, boolean, character,
string, severity_leveel, integer, real, natural, positive, time,
and the function NOW.
 package TEXTIO
with subprograms and types to support file input and output.
The contents of STANDARD and TEXTIO are available for use
within all designs without explicit USE statements.

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Special Library: WORK

 denotes the current working library during VHDL model

analysis.
 is typically selected either by a command to the VHDL
analyzer, or a directory selection at the system level.
Therefore, it can be a private library, or shared between
several users.
 Since the members of the WORK library are whatever
people have put into it, references to those packages,
entities, and architectures must be named by a USE
statement before the analyzer will be able to recognize
them.

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Special Library: IEEE

 library IEEE;
 use IEEE.std_logic_1164.all;
types, operators, and functions for detailed modeling
of logical data (of multivalued logic type)
 std_ulogic, std_logic, type conversion, overloaded operator

 use IEEE.std_logic_arith.all;
a set of arithemtic, conversion, and comparison
functions
 for SIGNED, UNSIGNED, SMALL_INT, INTEGER,
STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.

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Components

 To describe the interconnection of subsystems and the

use of different components
 Component declaration
component identifier [ is ]
[ generic ( generic_interface_list ); ]
[ port ( port_interface_list ); ]
end component [ identifier ];
 Component instantiation
instantiation_label:
[ component ] component_name
[ generic ( generic_interface_list ) ]
[ port ( port_interface_list ) ];

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Components: an example
entity reg4 is
port ( clock, clear:in bit; data:in bit_vector(0 to 3); qout:out bit_vector(0 to 3) );
end entity reg4;
--------------------------------------------------
architecture struct of reg4 is
component flipflop is
port ( clk : in bit; clr : in bit; d : in bit; q : out bit );
end component flipflop;
begin
gen : for i in 0 to 3 generate
bit: component flipflop
port map ( clk => clock, clr => clear, d => data(i), q => qout(i) );
end generate;
end architecture struct;

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Configuration

 Entity declaration and its architecture bodies

 Component declaration and instantiation
 use a design component (i.e. flipflop in reg4)
 A PC board example:
 place a socket on the board (define interface and
connect pins)
 nothing populates the socket

 Need a binding process to specify which entity we would

like to include in each component instance

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A Big Picture

 A design library contains design units (vhdl files)

 A design unit contains VHDL constructs (library units)

 primary library units: entity declaration, package
declaration, and configuration declaration
 second library units: architecture and package bodies
 context clause (i.e. library and use) preceding each
library unit specifies which other libraries it
references and which packages it uses.

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Configuration

 A design unit that describes the binding of entity interfaces to

component interface
 can be analyzed and as a target of a simulation
 Syntax rule
configuration identifier of entity_name is
for architecture_name
{ for component_specification
use ( entity_name ( architecture_idenifier)
| configuration configuration_name );
end for ; }
end for;
end [ configuration ] [ identifier ]

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Example: entity and architecture

entity Test is
port (S1, S2 : in bit; Q : out bit);
end Test;
architecture Structure of Test is
signal A, B, S : bit_vector(0 to 3);
component Nor2
port (I1, I2: in bit; O: out bit);
end component;
begin
Q1: Nor2 port map (I1 => S1, I2 => S2, O => Q);
Add: for i in 0 to 3 generate
Comp: Nor2 port map (I1 => A(i), I2 => B(i), O=> S(i));
end generate;
end Structure;

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Example: Configuration

configuration Config1 of Test is

use WORK.MyNor2; -- make "MyNor2" visible
for Structure -- configure arch. "Structure" of entity "Test"
for Q1: Nor2 use -- configure instance "Q1"
entity MyNor2(ArchX);
end for;
for Add -- config. instances created by for...generate
for all: Nor2 use -- config. all instances of comp."Nor2"
entity work.MyNor2(ArchY);
end for;
end for;
end for;
end Config1;

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What Do We Get From a Configuration

 Choices for low-level design entities in a design module

 plug in the chosen entities in the sockets
 select an architecture body for each chosen entity
 For hierarchical design
 choose a right configuration of a low-level design
entity
 When we need these choices
 models for behavior description, synthesizable FPGA
or ASIC designs
 design units for high-speed, low-power, high fan-out,
etc.

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Configuring Multiple Levels of
Hierarchy
configuration counter_down_to_gate_level of counter is
for registered
for all : digit_register
use configuration work.reg4_gate_level;
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration counter_down_to_gate_level;

 What are the relationships between

 counter. registered, digit_register, work.reg4_gate_level

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An Example:

entity example7 is -- direct instantiation of a design tree

end entity example7;
use work.counter_types.all;
architecture test of example7 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.counter_down_to_gate_level
generic map (tp=> 5 ns);
port map ( clk => clk, clr => clr, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns, '0' after 135 ns;
end architecture test;

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Port and Generic Maps

 Suppose we have two different memory chips (with

different delay and pins)
 chip 1 is used in the first design of computer_system
 chip 2 is used in the second design

 Can we have a generic design and two configurations

 to map chips 1 and 2 to the design, respectively

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Another Example

entity computer_system is
end entity computer_system;
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( p_delay : delay_length );
port ( in0, in1 : in bit; out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
begin
interface_decoder : component decoder_2_to_4
generic map ( p_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a, out1 => interface_b,
out2 => interface_c, out3 => interface_d);
-- . . .
end architecture structure;
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Example (continued)

 We cannot find a 2-to-4 decoder, but have a 3-to-8 decoder

entity decoder_3_to_8 is
generic ( Tp_01, Tp_10 : delay_length );
port ( s0, s1, s2 : in bit; enable : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;

 Can we use it in our computer_system

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Example (continued)

configuration computer_structure of computer_system is

for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tp_01 => p_delay, Tp_10 => p_delay )
port map ( s0 => in0, s1 => in1, s2 => '0', enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
end for;
end configuration computer_structure;

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Library Unit
entity t_flipflop is entity inverter is
port (clk : in bit; q : out bit); port (a : in bit; y : out bit);
end entity; end entity;
architecture model1 of t_flipflop is
signal t: bit :='0';
begin
latch: process (clk)
begin
if clk'event and clk='1' then
t <= not t;
q <= t;
end if;
end process;
end model1;

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Library Unit (continued)

architecture simple of inverter is

begin
y <= not a;
end simple;
-- package misc
package misc is
component t_flipflop
port (ck : in bit; q : out bit);
end component;

component inverter
port (a : in bit; y : out bit);
end component;
end package misc;
--
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Entity Declaration - count2

-- primary unit: entity declaration of count2

entity count2 is
generic (prop_delay : Time := 10 ns);
port (clock : in bit;
q1, q0 : out bit);
end count2;

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Architecture Behavior

-- secondary unit: a behavioural architecture body of count2

architecture behavior of count2 is
begin
count_up: process (clock)
variable count_value : natural := 0;
begin
if clock = '1' then
count_value := (count_value + 1) mod 4;
q0 <= bit'val(count_value mod 2) after prop_delay;
q1 <= bit'val(count_value / 2) after prop_delay;
end if;
end process count_up;
end behavior;

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Architecture Structure

-- secondary unit: a structural architecture body of count2

architecture structure of count2 is
component t_flipflop
port (clk : in bit; q : out bit);
end component;
component inverter
port (a : in bit; y : out bit);
end component;
signal ff0, ff1, inv_ff0 : bit;
begin
bit_0 : t_flipflop port map (clk => clock, q => ff0);
inv : inverter port map (a => ff0, y => inv_ff0);
bit_1 : t_flipflop port map (clk => inv_ff0, q => ff1);
q0 <= ff0;
q1 <= ff1;
end structure;

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Test Bench

entity test_count2 is -- primary unit: entity declaration of test bench

end test_count2;
architecture test_procedure of test_count2 is -- secondary unit:
signal clock, q0, q1 : bit;
component count2
port (clock : in bit; q1, q0 : out bit);
end component;
begin
counter : count2
port map (clock => clock, q0 => q0, q1 => q1);
clock_driver : process
begin
clock <= '0', '1' after 50 ns;
wait for 100 ns;
end process clock_driver;
end test_procedure;

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Testbench Configuration 1

-- primary unit: configuration using behavioural architecture

configuration test_count2_behavior of test_count2 is
for test_procedure -- of test_count2
for counter : count2
use entity work.count2(behaviour);
end for;
end for;
end test_count2_behavior;

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Testbench Configuration 2

-- primary unit: configuration using structural architecture

library misc_lib;
configuration test_count2_structure of test_count2 is
for test_procedure -- of test_count2
for counter : count2
use entity work.count2(structure);
for structure -- of count_2
for all : t_flipflop
use entity misc_lib.t_flipflop(model1);
end for;
for all : inverter
use entity misc_lib.inverter(simple);
end for;
end for;
end for;
end for;
end test_count2_structure;
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