8255
(Programmable Peripheral Interface)
Contents
• Introduction
• 8255 Functional Description
• 8255 pin diagram
• 8255 Internal Architecture
• 8255 Control Word Register (CWR)
• 8255 CWR for bit set/reset
• 8255 modes of operation
– Mode 0
– Mode 1
– Mode 2
• Mode definition summary
Introduction
• CMOS Programmable Peripheral Interface (PPI).
• It interfaces i/o device to the CPU.
• It is used for handshake and non-handshake
applications with i/o devices.
• It is a parallel port device.
• With the help of Control Word Register (CWR)
ports can be programmed as input or output.
8255 Functional Description
• 24 input/output lines
– Port A (8-bit input/output port, Bidirectional)
– Port B (8-bit input/output port)
– Port C (8-bit input/output port, 2 4-bit ports, to produce
handshake signals for Port A and B)
• 8 data lines
– write data bytes/control word to port or read data bytes/status
word from port
• Reset
– Initialize control register to 9Bh and all port as input port.
• Address inputs (A0, A1)
– Allows to access one of the 3 ports or the control word register.
– Port A: 00, Port B: 01, Port C: 10, Control Register: 11.
– System Address line A1 is connected to A0 and A2 to A1 of 8255.
8255 Pin Diagram
8255 Internal Architecture
8255 Control Word Register
8255 CWR for bit set/reset
8255 Modes of Operation
Mode 0
Mode 1(Strobbed input/output)
• Two Groups (Group A and Group B)
– Group A: Port A and Port C upper 4-bits.
– Group B: Port B and Port C lower 4-bits.
• Port A and Port B can be used as input or output port.
Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-
bit port.
Mode 1(Input)
• STB (Strobe input):
– a ‘low’ on this pin input loads data into the input latch.
• IBF (Input buffer full FF):
– A “high” on this output indicates that the data has been loaded
into the input latch.
– IBF is set by STB input being low and is reset by the rising edge
of the RD input.
• INTR (Interrupt Request)
– A “high” on this output can be used to interrupt the CPU
– INTR is set by the condition: STB is a “one”, IBF is a “one” and
INTE is a “one”. It is reset by the falling edge of RD.
• INTE:
– Controlled by PC4(A)/PC2 (B)
Mode 1 (Output)
• OBF (Output Buffer Full F/F):
– Low indicates CPU has written data to the specified port
– Will be set by the rising edge of the WR input and reset by ACK
input being low.
• ACK (Acknowledge input):
– Response from i/o device indicating that it is ready to accept the
data.
• INTR (Interrupt request):
– ‘high’ on this output, interrupt the CPU when the output device
accepted data sent by the CPU.
– It is ‘set’ when, OBF = 1, ACK = 1, INTE = 1.
• INTE:
– Controlled by PC6(A)/PC2 (B)
Mode 2 (strobed bidirectional bus i/o)
• Used in Group A only
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C).
• Both inputs and outputs are latched.
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A).
