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GAL16V8
(review seq_1.ppt)
• Each output is
programmable as
combinational or
registered And Plane
• Also has
programmable output
polarity XOR gates to
make inverting or
non-inverting buffer
A General CPLD structure
• The number of I/O pins are much less than the total number of
Macrocells in family of devices
Xinlinx CPLDs
Architecture of Xilinx 9500-family CPLD
36 Signal pins
18 outputs
Global Clock
Global set/reset 18 Output
enable signals
Global 3 state control
Architecture of Xilinx FB