CERN Technical Training 2005

ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics

Basic Analog Design

Giovanni Anelli
15 March 2005

Part II
ELEC 2005
 Outline – Part II

• Noise in analog ICs

• Matching in analog ICs
• Operational Amplifier design examples
• Analog design methodology

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 Thermal noise in passive components
Thermal noise is caused by the random thermally excited
vibration of the charge carriers in a conductor.

vn2 Power spectral density [ V 2 / Hz ]

R
vn2  4kTR  f [ V2 ]
in2

4kT
i 
2
n  f [ A2 ]
R R

There are no sources of noise in ideal capacitors or

inductors. In practice, real components have parasitic
resistance that does display thermal noise!
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 Noise sources in MOS transistors

Channel thermal noise: due to the random thermal motion of the

carriers in the channel
1/f noise: due to the random trapping and detrapping of mobile
carriers in the traps located at the Si-SiO2 interface and within the
gate oxide.
Bulk resistance thermal noise: due to the distributed substrate
resistance.
Gate resistance thermal noise: due to the resistance of the
polysilicon gate and of the interconnections.

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 Noise in circuits
To be independent from the gain of a given system, we use the concept
of input-referred noise. This allows comparing easily the noise
performance of different circuits (with different gains), and calculating
easily the Signal-to-Noise Ratio (SNR).
At the input of our linear two-port circuit, we use two noise generator
(one noise voltage source and one noise current source) to represent
the noise of the system regardless the impedance at the input of the
circuit and of the source driving the circuit.

v n2 ,in

Noisy Noiseless
v n2,out in2 ,in v n2,out
circuit circuit

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 Input-referred voltage noise
The MOS transistor is represented by its small-signal equivalent circuit.
We can refer the noise sources inside the MOS transistor to the input,
obtaining an input-referred voltage noise.

2 2
vin 1 Ka 1 gmb
 4kTng  2 
 4kTR G  4kT 2 RB
f gm Cox WL f gm
Channel thermal Gate resistance Bulk resistance
1/f noise
noise thermal noise thermal noise

g ideally varies from 1/2 (w.i.) to 2/3 (s.i.)

Ka = 1/f noise parameter, technology dependent

Usually, the first two terms are the most important

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 N-channel noise spectra
W = 2 mm, IDS = 0.5 mA, VDS = 0.8 V, VBS = 0 V
1.E-07
L = 0.36um
L = 0.5um
L = 0.64um
L = 0.78um
Noise [ V/sqrt(Hz) ]

L = 1.2um

1.E-08

1.E-09
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency [ Hz ]
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 Noise in a DP + Active CM
VDD VDD

2I 2I

2
vin 2
vin v 2tot

i2out i2out

2 2
vload vload

 g2
 2
v 2tot  2  vin  2   2
2 m _ load
  vload
 g 
 m _ in 
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 Noise in a DP + Active CM
1  K a _ load  load  Lin 
2
K a _ in
v 2
 2 2   1  f
VDD tot _ 1 / f
Cox WinLin f  K a _ in   in  Lload 
2 

2I

2
Make WinLin big and Lload  Lin
v tot

 W 
 load   
2   L load 
v 2tot _ th  4kTng   1   f
W W
2inCox in I  in   

Lin   L in 

W W
Make     
 L in  L load
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 Outline – Part II

• Noise in analog ICs

• Matching in analog ICs
• Operational Amplifier design examples
• Analog design methodology

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 The importance of matching
Yield of an N-bit flash Analog-to-Digital converter as a function of the
comparator mismatch

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 Relative & absolute mismatch
Mismatch occurs for all IC components (resistors,
capacitors, bipolar and MOS transistors)

D1
L1

D2
L2

L L2  L1 D  D1  D2 [m]

 200  [%]
L L2  L1

Relative mismatch Absolute mismatch

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 Mismatch in MOS transistors
Mismatch in physical parameters (Na, , Tox) and layout dimensions (W, L)
gives origin to mismatch in electrical parameters (VT, b and therefore ID)

Mismatch in
Na, , Tox

+
Mismatch in
W and L

Parameter b
VT and
IDS1 IDS2
mismatch b
I mismatch ID
VGS1 b VGS2 VGS and
IDS  ( VGS  VT )2 and V offset ID
2n
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 The golden rule: Bigger is better!

Random effects “average out” better if the area is bigger. Therefore,

for a given parameter P, we expect something like

 ΔP
AP
 ΔP 
WL AP
1/ WL [1/m]

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 Expected mismatch
Usually in a pair of identical transistors the two most important
parameter subject to mismatch are the threshold voltage Vth and the
current factor b

A Vth Ab
 Vth   b / b 
WL WL

AVth / tox ~ 1 mV·m / nm From the

Ab ~ 1 to 3 %·m literature

Mismatch can be treated as another source of noise. As in the noise

case, different “mismatch” sources can be grouped into one adding
the variances (not the standard deviations)

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 Differential pair mismatch
The two transistors have the same drain current
2
 I 
σ ΔVGS   2
Vth    b / b 
 gm 
22
σ VGS [mV ] 20
18 σ Δb/b  1.4 %
σ VT  4.5 mV
16

14

12

10

6
σ VT 4
2I 2

0
1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03

INVERSIONI.C.
COEFFICIENT
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 Current mirror mismatch
The two transistors have the same gate voltage
2
 gm 
σ ΔI/I   2
b / b   Vth 
 I 
14
σ ΔI/I [%]
12
σ Δb/b  1.4 %
10
σ VT  4.5 mV
I 8

σ b / b
2

0
1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03

I.C.
INVERSION COEFFICIENT
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 Offset of a DP + Active CM
RANDOM OFFSET (WORST CASE)
VDD
I  b1,2 b3,4 gm3,4 
v off  VT 1,2      V 

gm1,2  b1,2 b 3,4 I
T 3,4 

2I
SYSTEMATIC OFFSET
v off The difference in the drain voltages
Vin T1 T2 of T1 and T2 gives origin a difference
in the DC currents in the two
Vout branches.

T3 T4 “COMMON MODE” OFFSET

Due to mismatches in the transistors,
a common mode signal at the input
gives a non zero output voltage
signal.

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 Outline – Part II

• Noise in analog ICs

• Matching in analog ICs
• Operational Amplifier design examples
 Op Amp application examples
 Single-Stage Op Amps
 Two-Stage Op Amps
 Fully Differential Op Amps
 Feedback and frequency compensation
• Analog design methodology

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 The ideal op amp
An op amp is basically a voltage-controlled voltage source

Vin +

Rout
Rin A0 (vin  vin ) Vout

Vin -

The op amp is ideal when

A0 = Rin = ∞, Rout = 0

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 Op amp application examples
NONINVERTING INVERTING
CONFIGURATION CONFIGURATION
R2
Vin
Vout

Vin
Vout
R1
R2 BUFFER
R1

Vin
Vout = Vin

R R2
G  1 2 G
R1 R1
G1

The above equations are valid only if the gain A0 of the op amp is very high!
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 Single-stage Op Amp
VDD
The differential pair + active current
mirror scheme we have already seen is a
T7 T8
single stage op amp. Several different
solutions can be adopted to make a
T5 T6 Single-stage amplifier. If high gains are
needed, we can use, for example,
Vout cascode structures.
With single-stage amplifiers it is difficult
Vb1 T3 T4 Vb1
to obtain at the same time high gain and
voltage excursion, especially when
T1 T2 other characteristics are also required,
Vin such as speed and/or precision.
Two-stage configurations in this sense
ISS are better, since they decouple the gain
and voltage swing requirements.

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 Two-stage Op Amp
G  gm2 (r02 // r04 )  gm5 (r05 // r08 )

VDD
The second stage is
T6 T7 T8
very often a CSS,
since this allows the
maximum voltage
Vout swing.
Vin - T1 T2 Vin + The output voltage
swing in this case is
Rb VDD - |2VDS_SAT|

T5
T3 T4

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 Two-stage Op Amp
G  gm1,2 (r01,2 // r03 ,4 )  gm6 (r06 // r08 )
VDD

T3 T4
In this case we kept the
T5 Vb T6 differential behavior of
the first stage, and is the
current mirror T7-T8
T1 T2
which does the
Vin differential-to-single
Vout ended conversion. The
output is still a CSS.
ISS

T7 T8

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 Fully Differential Op Amp
G  gm1,2 (r01,2 // r03 ,4 )  gm5,6 (r05 ,6 // r07 ,8 )
VDD

T3 T4

T5 Vb1 T6

T1 T2
Vin
Vout1 Vout2
ISS

T7
Vb2 T8

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 Fully Differential Op Amp
G   gm1,2 (gm3,4  gmb 3,4 )r03 ,4r01,2 ) // (gm5,6  gmb 5,6 )r05 ,6r07 ,8 )  gm9,10 r09 ,10 // r011,12 
VDD
To increase the
T7 T8 gain, we can again
Vb3 Vb3
make use, in the
first stage, of
Vb2 T5 T6 Vb2 cascode structures.
T9 T10

Vb1 T3 T4 Vb1

Vout1 T1 T2 Vout2

Vin

Vb4 T11 ISS T12 Vb4

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 Feedback

Vin
e Vout
+ A(s)
vout (s) A(s) A(s)
G(s)   
vin (s) 1  A(s)F(s) 1  Gloop (s)
F(s)

• A(s) is the open loop transfer function

• F(s) is the feedback network transfer function
• G(s) is the closed loop transfer function
• A(s)F(s) is the loop gain
• If the feedback is negative, the loop gain is negative

• For |Gloop(s)| >> 1, we have that 1

G(s)  
F(s)
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 Properties of negative feedback
Negative feedback reduces substantially the gain of a circuit, but it
improves several other characteristics:
• Gain desensitization: the open loop transfer function is generally
dependent on many varying quantities, given by the active components
in the circuit. Using a passive feedback network, we can reduce the
dependence of the gain variation on the variations of the open loop
transfer function.
dG dA 1

G A 1  Gloop

• Reduction of nonlinear distortion

• Reduction or increase (depending on the feedback topology) of the
input and output impedances by a factor 1-Gloop.
• Increase of the bandwidth

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 Bode diagrams
Many interesting properties of the frequency behavior of a given circuit can be
obtained plotting the module and the phase of the Transfer Function as a
function of the frequency. These plots are called Bode diagrams. In the general
case, a transfer function is given by the ratio between two polynomials. The
roots of the numerator polynomial are called zeros, the roots of the
denominator polynomials are called poles. For example, in the case of a
low-pass filter with RC = 1 ms, the Bode diagrams look like:
20 0

-10

-20
20log 10 |H(s)| [dB]

Phase [degrees]
0
-30

-40
-20
-50

-60
-40 -70

-80

-60 -90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency [rad/s] Frequency [rad/s]

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 Bandwidth increase with feedback
|G(s)|
A0
A ( s) 
Vin Vout s
A0 1
+ A(s) w0

A0 1

1  fA 0 f
-f
w
w0 w0(1+fA0)
GBWP
A0
A ( s) 1  fA 0
G(s)  
1  f  A ( s) 1  s
(1  fA 0 )w0

The gain-bandwidth product does not change with feedback!

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 Stability Criteria
|fA(s)| GREEN: STABLE
Vin Vout
+ A(s) RED: UNSTABLE

-f
w1 w1
G(s) 
A(s) w
1  f  A(s)  fA(s)
1  f  A(s)  0
w
Barkhausen’s Criteria - 90
|fA(jw1)| = 1 - 180

 fA(jw1) = - 180

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 Phase Margin
We have seen that to ensure stability |fA(s)| must be smaller than 1 before
 fA(s) reaches - 180. But, in fact, to avoid oscillation and ringing, we
must have a bit more margin.
We define phase margin (PM) the quantity 180 +  fA(w1), where w1 is the
gain crossover frequency. It can be shown that, to have a stable system
with no ringing (for small signals) we must have PM > 60. If we want to
have an amplifier which responds to a large input step without ringing,
PM must be even higher.

|fA(s)| |fA(s)|
w1 w1
w w
SMALL PM LARGE PM
 fA(s)  fA(s)
w w
- 180 - 180

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 Frequency Compensation

Single-pole op-amps RED: BEFORE COMPENSATION

|fA(s)|
GREEN: AFTER COMPENSATION
would always be stable
(the phase does not go
below - 90). But a typical
op-amp circuit always
contains several poles
(and zeros!). These op-
amps can easily be w1 w1
unstable, and they need
therefore to be  fA(s)
compensated. This is
generally done lowering
the frequency of the - 90
dominant pole. - 180

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 Outline – Part II

• Noise in analog ICs

• Matching in analog ICs
• Operational Amplifier design examples
• Analog design methodology

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 Analog design methodology

Define specifications
Extract schematic from
layout
Choose architecture
Layout Versus Schematic
(LVS) check
Simulate schematic

Extracted schematic
Simulate schematic varying
simulations
T, VDD, process parameters

Masks layout BLOCK DONE!

In a complex design,
Design Rules Check (DRC) this will be repeated
for every block of the
design hierarchy.
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 Analog design trade-offs

NOISE LINEARITY

POWER
GAIN
DISSIPATION
ANALOG
DESIGN
INPUT/OUTPUT
OCTAGON SUPPLY
IMPEDANCE VOLTAGE

VOLTAGE
SPEED
SWINGS

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 Bibliography
Books:
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.
P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001.
R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.
R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990.
D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.
Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999.
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.
C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, John Wiley and Sons, 1993.
A. L. McWhorter, Semiconductor Surface Physics, University Pennsylvania Press, 1956, pp. 207-227.
Z.Y. Chang and W.M.C. Sansen, Low-noise wide-band amplifiers in bipolar and CMOS technologies, Kluwer Academic Publishers, 1991.

Papers:
K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision
Analog Design", IEEE Journal of Solid-State Circuits (JSSC), vol. 21, no. 6, December 1986, pp. 1057-1066.
Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", JSSC, vol. 34, no. 3, March 1999, p. 268.
M.J.M. Pelgrom et al., “Matching Properties of MOS Transistors”, IEEE JSSC, vol. 24, no. 10, 1989, p. 1433.
M.J.M. Pelgrom et al., “A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application”, IEEE JSSC, vol. 29, no. 8, Aug. 1994 , pp. 879-886.
R. W. Gregor, "On the Relationship Between Topography and Transistor Matching in an Analog CMOS Technology", IEEE Transactions on
Electron Devices, vol. 39, no. 2, February 1992, pp. 275-282.

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 CERN Technical Training 2005

ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics

Basic Analog Design

Giovanni Anelli
15 March 2005

Part II
ELEC 2005