Laboratório de Telecomunicações

Departamento de Engenharia Elétrica

Universidade Federal do Espírito Santo

FPGA Implementation of an
OFDM Modem
http://www.labtel.ele.ufes.br

Tonny M. Siqueira and Evandro O. T. Salles

Why OFDM (Orthogonal Frequency Division Multiplexing)?

Fully digital modulation
~50% bandwidth reduction
Multipath robustness and ease channel equalization
Applications: Digital TV, ADSL, VDSL, PLCC, Wi-Fi, UWB
Why FPGA?
Rapid prototype design flow
FPGA vs. DSP for Wi-Fi implementation
• Wi-Fi needs 15 GOPS
• Texas Instruments C64x DSP less than 5 GOPS
• Virtex can support up to 20 GOPS
 OFDM System
Cyclic-prefix

m0
bits

m1
a0+jb0
Transmitter

Paralell/Serial Conversion
Serial/Paralell conversion
bits a1+jb1

m2

Symmetry
http://www.labtel.ele.ufes.br

Hermitian
Encoder
bits a2+jb2

IFFT
D/A
M-bit stream Data
...

...
data input Output

...
mN-1
bits aN-1+jbN-1
Spectral Compression

Eliminating hermitian
simmetry Eliminating cyclic-prefix

m0
f
bits Orthogonality
between subcarriers
m1
Paralell/Serial Conversion

bits Parallel/Serial Conversion OFDM Spectrum

a0+jb0
m2
Decoder

bits a1+jb1
FFT

A/D
M-bit stream Signal
...

Data Output a2+jb2 input

...

...

mN-1
bits aN-1+jbN-1

Receiver
 Our approach to
Implemented through CORDIC
(Coordinate Rotation Digital Computer) OFDM system
Efficient and flexible Divider
Multiplicator
Twiddle
http://www.labtel.ele.ufes.br

Limiter Factor
FFT implementation Dual
Port
Ram
Dual
Hermitian
Adder Port
symmetry
Ram Real data
Dual output
Serial/
Encoder Port
Parallel mn bits Complex Ram
block data
input input

Twiddle Divider
Multiplicator
Factor Limiter
Synchronizer
Serial
Port Dual
Port
Ram
Dual
Parallel/
Decoder Port Adder
Serial mn bits Complex Ram
block data Dual
output output Port
Ram Real data
input

RTL Controller Circuits optimized for 64-point FFT (i.e. up to 31 subcarriers)

 Design improvements

Coregen Our approach

CORDIC Maximum Frequency
http://www.labtel.ele.ufes.br

CORDIC (12-bit / 8-pipeline)

110
35
30 100
FPGA utilization [%]

25
90
20

MHz
80
15
10 70

5 60
0
50
Slices Flip-Flops

FFT (12-bit / 64-point) FFT maximum frequency

80 75
70
FPGA utilization [%]

70
60 65
50 60
55
MHz

40
30 50

20 45
40
10
35
0
30
Slices Flip-Flops Block RAM
 FPGA utilization
(Final design - Spartan IIE)
Modem capacity: 12 bit / 64 point FFT, up to 14.3Mbps at 50 MHz clock.

Full System (31 subcarriers)

http://www.labtel.ele.ufes.br

Maximum Frequency - 93.5 MHz

100
FPGA Utilization [%]

80

60

40

20

0
Slices Flip-Flops Block RAM

Future Work: Synchronization, Error Corrections (TCM, Interleaving, Turbo Coding), Other basis
different from DFT (ELT – Extended Lapped Transform, WPM – Wavelets Packets Modulation).