RC Delay Model

Transistors are assumed to have an internal resistance R.

R varies with the mode of operation hence it is taken as the ratio
𝑉𝑑𝑠 Τ𝐼𝑑𝑠 . This resistance in a circuit is taken to be associated with
the smallest transistor. A unit nMOS. It has a minimum length and
width ( 4Τ2 𝜆). If the width of a transistor is k times that of the unit
transistor its resistance is 𝑅Τ𝑘. pMOS, due to its higher hole
mobility compared to electron is taken to have a resistance 2R. 𝑅 ≈
10k.
A transistor operating under velocity saturation conditions ( high 𝑉𝑑𝑠 ) has a higher
resistance since the current does not change much with voltage. However we know
that 𝑉𝑑𝑠 is not large for transistors operating in series. Therefore they have lower
resistance.
Capacitance C is taken for the gate of the unit transistor. The same is taken for the
source and drain. Since the area and perimeter of the source/drain regions increase
on increasing the width, the capacitance associated increases. If the width is k
times the unit width the capacitance is kC. Capacitance generally depend on
voltages. C is taken to be 1fF/mm width.
A 3-input NAND gate and equivalent circuit is shown.

The width of each nMOS in series is adjusted to give

The same resistance when combined equal to R. The

parallel connected pMOS width is also doubled to get
R.
 Transient Response

This is the ratio 𝑉𝑜𝑢𝑡 Τ𝑉𝑖𝑛

1
𝐻 𝑠 =
1 + 𝑠𝑅𝐶
s is a complex number having the dimension of inverse
time
For a step input assuming initially uncharged capacitor
The Laplace transform of input is
∞
𝑠𝑡
𝑉𝐷𝐷
න 𝑉𝐷𝐷 𝑒 𝑑𝑡 =
0 𝑠
To obtain the output we have to take the inverse Laplace
transform of 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟 𝑓𝑢𝑛𝑐𝑡𝑖𝑜𝑛 × 𝑖𝑛𝑝𝑢𝑡
Two methods
1. Using partial fractions and tables
2. Applying the concepts of calculus of residue
 𝑉𝐷𝐷
• 𝑉𝑜𝑢𝑡 =L-1𝐻(𝑠)
𝑠
1 1 1
• 𝐻 𝑠 = − 1
𝑠 𝑠 𝑠+
𝑅𝐶
𝑡
−
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 1 − 𝑒 𝑅𝐶

Similarly the decay of a capacitor can be obtained by using the initial condition that the
capacitor is charged and there is no applied potential source.
𝑡
−𝑅𝐶
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 𝑒

Notice that the logic low threshold 𝑉𝐷𝐷 Τ2 is obtained at the time
𝑡𝑝𝑑 = 𝑅𝐶 ln 2
𝑡𝑝𝑑 = 0.693𝑅𝐶