ELE615

SEMICONDUCTOR FABRICATION
TECHNOLOGY
MINI PROJECT

PREPARED BY:
- MUHAMMAD HANAFI AKMAL BIN ABDUL RAHMAN
- MUHAMMAD ASYRAAF BIN GELAN
-MUHAMMAD AMIR LUQMAN BIN MOHAMAD SUJANA
INTRODUCTION
• Technology Computer Aided Design(CAD) is a branch of electronic
design automation that models semiconductor fabrication and
semiconductor device operation.
• modeling fabrication is termed Process TCAD(ATHENA In SILVACO)
• modeling of the device operation is termed Device TCAD(ATLAS In
SILVACO)
INTRODUCTION
• How SILVACO works?
SILVACO

Input text output.STR

command file
DECKBUILD ATHENA ATLAS

TONYPLOT
OBJECTIVES
1. To introduce and utilize the process and device simulation tools :
Silvaco TCAD – ATHENA & ATLAS
2. To understand the effects of each process steps on the device
fabrication and performance through investigation and simulation
results of NMOS device.
3. To identify step where the source and drain doping, vary the
parameter dose or energy to observe the effect of source and drain
implant annealing.
Problem statement
(Doping and drive-in effect of source and drain in
NMOS):
1. Investigate how the source and drain doping affecting the
performance of the NMOS?
2. Investigate how the drive in(annealing) to the source and drain
doping affecting the device performance. Show the doping
concentrations( label the surface and peak concentration) before
and after the drive-in process. Extract junction depth before and
after the drive-in.
Source and drain doping investigation is here.
We will Investigating the effect of source and
drain doping and its drive-in(annealing) effect.
BASIC NMOS PROCESS FLOW
PROCESS SIMULATION
STEP 1
This process are to initiate silicon
substrate. To show the result in 2
dimension, “two.d” command are write in
the text window
STEP 2
STEP 3
This process show the etch silicon
oxide with thickness of 0.02 at the
substrate
STEP 4
STEP 5
STEP 6
STEP 7
STEP 8
STEP 9
STEP 10
STEP 11
STEP 12
STEP 13
STEP 14
STEP 15
STEP 16
STEP 17
STEP 18
STEP 19
STEP 20
STEP 21
STEP 22
RESULTS
TonyPlot of the NMOS with different value of
Energy
Energy at 50 kev Energy at 100 kev
TonyPlot of the NMOS with different value of
Energy
Energy at 150 kev
junction depth(Xj), n++ sheet resistance, LDD
sheet resistance, long channel threshold voltage
Energy(kev) Junction n++ sheet LDD sheet Long channel Oxide
depth(Xj) resistance resistance threshold voltage thickness, tox

50 kev 0.1843um 29.093um 2276.8um 0.6106v 110.16um

100 kev 0.546um 23.06um 941.39um 0.533v 110.16um

150 kev 0.4619um 19.628um 282.313um -9.529x10^24v 110.16um

RESULTS
DEVICE SIMULATION
Energy at 50 kev

ID Vs VD ID Vs VG
RESULTS
DEVICE SIMULATION
Energy at 100 kev

ID Vs VD ID Vs VG
RESULTS
DEVICE SIMULATION
Energy at 150 kev

ID Vs VD ID Vs VG
RESULTS
DEVICE SIMULATION
Combination 50, 100, 150 (kev)