 Instruction Format

 Addressing Mode

K. Santhi
SITE, VIT
 Instruction Formats
• Fields in Instruction Formats
1) Operation Code Field : specify the operation to be
performed
2) Address Field : designate a memory address or a
processor register
3) Mode Field : specify the way to determine operand or
the effective address (Addressing Mode)
• Instruction Format with mode field :
 Instruction Format

INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU

- The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
THREE, and TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions:

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
 1) Three-Address Instruction
cont..

. . CPU

Op1Addr: OP1

Op2 Addr: OP2. +

Bits: 8 24
Add Res, Op1, Op2
(Res <- Op1 + Op2)

24 24
Opcode Res Addr Op1 Addr Op2 Addr
ResAddr: Res

Program 24
Nexti Addr: Nexti Counter
 2) Two-Address Instruction cont..

. . CPU Add Op1, Op2

(Op2 <- Op1 + Op2)
Op1Addr:

Op2Addr:
OP1

.
OP2, Res
+
Bits: 8
Opcode
24
Op1 Addr
24
Op2 Addr

Program 24
Nexti Addr: Nexti Counter
ONE, and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
3) One-Address Instruction

Op1Addr:
. .
OP1 +
CPU
Add Op1
(Acc <- Acc + Op1)

. Accumulator
Bits: 8
Opcode
24
Op1 Addr

Program 24
Nexti Addr: Nexti Counter
 push Op1 Add (TOS <- TOS + SOS)
(TOS <- Op1)
Bits: 8
Bits: 8 24 Opcode
Opcode Op1 Addr

CPU

Op1 Addr: ●●
OP1

TOS ●
+
SOS
TOS

Stack
Program 24
Nexti Addr: Nexti Counter
 RISC Instruction
• Reduced instruction set computer
• RISC processor
– Only use LOAD and STORE inst.
• Transfer between memory and CPU
• Have 1 reg. and 1 memory address
– All other insts
• Executed within the registers of the CPU without
referring to memory
• Have 3 addresses.
Program to evaluate X = ( A + B ) * ( C + D )
Assignment
 Write a program to evaluate the arithmetic statement:
 Using a general register computer with three address instructions
 Using a general register computer with two address instructions
 Using an accumulator type computer with one address instructions
 Using a stack organized computer with zero-address operation
instructions

A  B  C * (D * E  F )
X 
G  H *K
K. Santhi
SITE,VIT
 Problems
 Find the effective address and the content of AC for the given
data.

V.Saritha, SCSE, VIT University

Addressing Mode Effective Content of AC
Address
Direct Address 500 AC ← (500) 800
Immediate operand 201 AC ← 500 500
Indirect address 800 AC ← ((500)) 300
Relative address 702 AC ← (PC + 500) 325
Indexed address 600 AC ← (XR + 500) 900
Register - AC ← R1 400

Register Indirect 400 AC ← (R1) 700

Autoincrement 400 AC ← (R1)+ 700
Autodecrement 399 AC ← -(R1) 450
  Assume that in a certain byte-addressed machine all
instructions are 32 bits long. Assume the following state of
affairs for the machine: Fill in the following table:

Address Value Instruction Addressing Value in R0

mode
PC 100 Immediate
Load r0, #200
R0 200 Load r0, 200 Direct
R1 300
Load r0, (200) Indirect
100 200 Load r0,r1 Register
104 300 Load r0, [r1] Register Indirect
108 400 Load r0, -100[r1] Based
200 500 Load r0, 200[PC] Relative

300 600

500 700
Instruction types
 Data transfer instructions
 Data manipulation instructions
 Arithmetic instructions
 Logical and bit manipulation instructions
 Shift instructions
 Program control instructions
Data transfer instructions
 Move data from one place to another without changing
the data content in the computer.
 Different data transfers:
 Memory ↔ processor registers
 Processor registers ↔ input or output
 Processor register ↔ processor register
Set of data transfer instructions
 Load – transfer from memory to a processor register
 Store – transfer from processor register into memory
 Move – transfer from one register to another, transfer
between register and memory or between two memory
words.
 Exchange – swaps information between two registers or a
register and a memory word
 Input – transfer data among registers and input terminal
 Output – transfer data among register and output terminal
 Push – transfer data from register to memory stack
 Pop – transfer data from stack to register
 Data Manipulation Instructions
 Perform operations on data and provide the computational
capabilities for the computer.
 Arithmetic instructions
 Increment
 Decrement
 Add
 Subtract
 Multiply
 Divide
 Add with carry
 Subtract with borrow
 Negate (2’s complement) – change the sign of the operand
 Absolute – replace operand by its absolute value
 Arithmetic shift left
 Arithmetic shift right
 Arithmetic shift left

0 0 0 1 1 0 1 0

Sign bit

0 0 0 1 1 0 1 0 Shift by 1 bit towards left

Sign bit
0

0 0 1 1 0 1 0 0 After shifting two times

Sign bit
0

After shifting three times

0 1 1 0 1 0 0 0

Overflow occurs as
Sign bit sign bit changes
0
 Arithmetic shift Right: -ve values are in 2’s complement form

1 0 0 1 1 0 1 0

Sign bit

1 0 0 1 1 0 1 0 Shift by 1 bit towards right

Sign bit

1 1 0 0 1 1 0 1 After shifting two times

Sign bit

After shifting three times

1 1 1 0 0 1 1 0

Sign bit
Data manipulation instructions
 Logical and Bit manipulation instructions
 Clear (can also be included in data transfer instruction based on the
way the operation is performed – 0’s transferred to the destination)
 Complement
 AND – to clear selected bits
 OR – to set selected bits
 Ex-Or – to complement selected bits
 Clear carry
 Set carry
 Complement carry
 Enable interrupt – flip-flop that controls the interrupt facility is
enabled
 Disable interrupt – flip-flop that controls the interrupt facility is
disabled
Data manipulation instructions
 Shift Instructions
 Logical left shift
 Logical right shift
 Arithmetic shift left
 Arithmetic shift right
 Rotate right
 Rotate left
 Rotate right through carry
 Rotate left through carry
 Logical shift left

0 0 0 1 1 0 1 0

0 0 0 1 1 0 1 0 Shift by 1 bit towards left

0 0 1 1 0 1 0 0 After shifting two times

After shifting three times

0 1 1 0 1 0 0 0

0
 Logical shift Right

0 0 0 1 1 0 1 0

0 0 0 0 1 1 0 1 0 Shift by 1 bit towards right

0 0 0 0 0 1 1 0 1 After shifting two times

After shifting three times

0 0 0 0 0 0 1 1 0
 Rotate left

0 0 0 1 1 0 1 0

0 0 0 1 1 0 1 0 Rotate by 1 bit towards left

Buffer

0 0 1 1 0 1 0 0 After rotating two times

Buffer

After rotating three times

0 1 1 0 1 0 0 0

Buffer
 Rotate right

0 0 0 1 1 0 1 0

rotate by 1 bit towards right

0 0 0 1 1 0 1 0
Buffer

0 0 0 0 1 1 0 1 After rotating two times

Buffer

After rotating three times

1 0 0 0 0 1 1 0

Buffer
 Rotate left through carry

0 0 0 1 1 0 1 0

Rotate by 1 bit towards left

0 0 0 1 1 0 1 0 0
Buffer Carry

0 0 1 1 0 1 0 0 0 After rotating two times

Buffer Carry

After rotating three times

0 1 1 0 1 0 0 0 0

Buffer Carry
 Rotate right through carry

0 0 0 1 1 0 1 0

rotate by 1 bit towards right

0 0 0 0 1 1 0 1 0
Carry Buffer

0 0 0 0 0 1 1 0 1 After rotating two times

Carry Buffer

After rotating three times

0 1 0 0 0 0 1 1 0
Carry
Buffer
Program control Instructions
 Branch
 Jump
 Skip
 Call
 Return
 Compare (by subtraction)
 Test (by ANDing)
References
 M. M. Mano, Computer System Architecture,
Prentice-Hall
 J. P. Hayes, Computer system architecture, McGraw
Hill
Subroutine
 Subroutine is a self-contained sequence of instructions that
performs a given computational task.
 It may be called many times at various points in the main
program
 When called, branches to 1st line of subroutine and at the
end, returned to main program.
 Different names to the instruction that transfers program
control to a subroutine
 Call subroutine
 Jump to subroutine
 Branch to subroutine
 Branch and save address
Control transfer from called to caller
 Subroutine instruction – Opcode + starting
address of the subroutine
 Execution:
 PC content (return address) is stored in a temporary
location
 Control is transferred to the subroutine
 when return
 Transfers the return address from the temporary
location to the PC.
 Control is transferred back to the called routine
Locations to store the return address
 First memory location of the subroutine
 Fixed location in memory
 Processor registers
 Memory stack – best option
 Adv: In the case of sequential calls to subroutines. So,
the top of the stack always has the return address of the
subroutine which to be returned first.
 Micro-operations
Call:
SP ← SP – 1 // decrement stack pointer
M[SP] ← PC // push content of PC onto the stack
PC ← effective address /* transfer control to the subroutine
*/

Return:
PC ← M[SP] // pop stack and transfer to PC
SP ← SP + 1 // increment stack pointer
Recursive subroutines
 Subroutine that calls itself
 If only one register or memory location is used to hold
the return address, when subroutine is called
recursively, it destroys the previous return address.
 So, stack is the good solution for this problem
Registers
 Memory Hierarchy
 Registers
 Cache memory
 Main memory
 Secondary memory
 At higher levels of hierarchy, memory is faster, smaller and
more expensive.
 Number and function vary between processor designs - one
of the major design decisions
 Top level of memory hierarchy
 Two roles
 User-visible registers
 Control and status registers
User-Visible Registers
 General Purpose
 Data
 Address
 Condition Codes
General Purpose Registers
 True general purpose registers – register can contain the
operand for any Opcode
 Restricted – used for specific operations – floating point
and stack operations. (dedicated registers)
 Data registers – used only to hold data and cannot be
employed in the calculation of an operand address –
Accumulator (AC)
 Address registers
 Segment registers – holds the address of the base of the segment.
 Index registers – used for indexed addressing and may be auto-
indexed
 Stack pointer – points to the top of the stack (if there is a user-
visible stack addressing, stack is in memory)
Design Issues
 Specialized registers
 Implicit in the Opcode, Saves bits (small instructions) –
because of less number of specialized registers, Less
flexibility
 General purpose registers
 Increased instruction size, increased flexibility and
programmer options
 Fewer registers result in more memory references
Control & Status Registers
 Not visible to the user
 May be visible in a control or operating system
mode (supervisory mode)
 Registers essential to instruction execution:
 Program Counter (PC)
 Instruction Register (IR)
 Memory Address Register (MAR) – connects to address
bus
 Memory Buffer Register (MBR) – connects to data bus,
feeds other registers
Program Status Word
 Contains status information
 Condition Codes:
 Sign (of last result)
 Zero (last result)
 Carry (multiword arithmetic)
 Equal (two latest results)
 Overflow
 Interrupts enabled/disabled
 Supervisor/user mode
Example Register
Organizations
Register Files (RF)
 Set of general purpose registers.
 It functions as small RAM and implemented using
fast RAM technology.
 RF needs several access ports for simultaneously
reading from or writing to several different
registers. Hence RF is realized as multiport RAM.
 A standard RAM has just one access port with an
associated address bus and data bus.
 A register file with three access ports -
symbol

Data in C
16
2
Address C Port C

Register File
RF
2 2
Address A Port A Port B Address B

16 16
Data out A Data out B
A Register File with three access ports – logic diagram
Ex: R3 ← R1 + R2
Data in C Read Address A = 01
16 Read Address B = 10
Write 11 2 Write Address C = 11
4-way 16-bit
address C S demultiplexer

16 16 16 16

16-bit register R3 16-bit register R2 16-bit register R1

0101 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

01 S multiplexer multiplexer S
Read Read
address A 16 16 address B
Data out A
Data out B
A Register File with three access ports – logic diagram
1011 Ex: R3 ← R1 + R2
Data in C Read Address A = 01
16 Read Address B = 10
2 Write Address C = 11
Write 11 4-way 16-bit
S demultiplexer
address C

16 16 16 16

16-bit register R3 16-bit

0110register R2 16-bit register R1
0101 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

01 S multiplexer multiplexer S 10
Read Read
address A 16 16 address B
Data out A
Data out B
Quiz
 If the 8 registers are used
 How many bits are needed for read/write address?
 What is the size of the demultiplexer and multiplexer
required?
 If 4 multiplexers are used, how many parallel reads
can be performed?
 If 2 demultiplexers are used, how many parallel
writes can be performed?
 Give an example with 4 parallel reads and 2
parallel writes.(how many registers are required?)
References
 W. Stallings, Computer organization and
architecture, Prentice-Hall,2000
 J. P. Hayes, Computer system architecture, McGraw
Hill
References
 M. M. Mano, Computer System Architecture, Prentice-
Hall