Testbenches

Automating Design Verification

Vipin Kizheppatt 23/10/2019

 Design Verification
• Verification is a very important step during system
design
• As a thumb rule, 20% of development time is spent on
design and 80% on verification
• Verification of Verilog designs is done through
simulation
• We have already done this with the integrated
simulator available with Vivado
• There are other simulation tools also such as
ModelSim, QuestaSim, NC-Sim, Icarus Verilog etc.
 Design Verification
• Last time when we did simulation, we verified the
correctness of our design through wave forms
• We forced the input signals to known values (including
clock) and manually verified whether expected output
is out
• For small designs this perfectly works, but when
designs become complex with hundreds of inputs and
thousands of output, such manual verification through
waveform before impossible
• We need to implement some kind of automation in
this regard
 Testbenches
• Testbenches help us to improve design verification
• Testbenches emulate the environment around the
system which needs to be tested
• Hence the system which is being tested is usually called
Design Under Test (DUT) or Unit Under Test (UUT)
• Every input to the DUT comes from the external
environment (in this case Testbench) and every output
goes back to the testbench
• There may be a separate logic in the testbench which
compares the output from the DUT with the expected
output and decides whether DUT works correctly or
not
 Testbenches
Testbench

Input Output
generator DUT Monitor

Verification
Logic
 Testbenches
• Testbenches can be written using HDL languages
(Verilog, VHDL) or high-level languages (C/C++) or
specialized languages for verification (e/Vera)
• We will write our testbenches in Verilog itself
• Keep in mind that testbench codes are used only for
simulation
• They will not be implemented on real hardware
• Hence we have more flexibility in coding style and
more constructs are available compared to the code
targeted for hardware implementation
 Testbenches
• Hence we will divide the Verilog code that we write
into two categories
– Synthesizable  which can be finally implemented
on FPGA/ASIC
– Non-synthesizable  which cannot be implemented
on real hardware but can be used for simulation
• Now a days the term RTL code is used
synonymously for synthesizable code (although
original meaning was different)
• Testbenches will be commonly referred as TB