WATCH DOG TIMER

PRESENTED BY,
GOKULNATH N – 18L432
SACHIN S -18L440
CONTENTS
 INTRODUCTION
 FEAUTURES
 BLOCK DIAGRAM
 REGISTER ACCESS TIMING
 INITIALIZATION AND CONFIGURATION
 REGISTER MAP
INTRODUCTION
• WATCH DOG TIMER is an electronic timer that is used to detect
and recover from computer malfunctions.

• In other words , watchdog timer is used to regain control when a

system has failed due to a software error or due to the failure of
an external device

• The TM4C123GH6PM microcontroller has two Watchdog Timer

Modules, one module is clocked by the system clock (Watchdog
Timer 0) and the other (Watchdog Timer 1) is clocked by the
PIOSC

• The two modules are identical except that WDT1 is in a different

clock domain, and therefore requires synchronizers
FEAUTURES
The TM4C123GH6PM controller has two Watchdog Timer modules with the
following features,

 32-bit down counter with a programmable load register

 Separate watchdog clock with an enable
 Programmable interrupt generation logic with interrupt masking
and optional NMI function
 Lock register protection from runaway software
 Reset generation logic with an enable/disable
 User-enabled stalling when the microcontroller asserts the CPU Halt flag
during debug
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
 The Watchdog Timer module generates the first time-out signal when the
32-bit counter reaches the zero state after being enabled; enabling the
counter also enables the watchdog timer interrupt.

 The watchdog interrupt can be programmed to be a non-maskable interrupt

(NMI) using the INTTYPE bit in the WDTCTL register.

 If the timer counts down to its zero state again before the first time-out
interrupt is cleared, and the reset signal has been enabled by setting the
RESEN bit in the WDTCTL register, the Watchdog timer asserts its reset
signal to the system
FUNCTIONAL DESCRIPTION(CONT..)
 If the interrupt is cleared before the 32-bit counter reaches its second time-
out, the 32-bit counter is loaded with the value in the WDTLOAD register,
and counting resumes from that value.

 If WDTLOAD is written with a new value while the Watchdog Timer counter is
counting, then the counter is loaded with the new value and continues
counting.

 The Watchdog module interrupt and reset generation can be enabled or

disabled as required. When the interrupt is re-enabled, the 32-bit counter is
preloaded with the load register value and not its last state.
REGISTER ACCESS TIMING
 The Watchdog Timer 1 module has an independent clocking domain, its
registers must be written with a timing gap between accesses.

 Software must guarantee that this delay is inserted between back-to-back

writes to WDT1 registers or between a write followed by a read to the
registers.

 The timing for back-to-back reads from the WDT1 module has no restrictions.
The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates
that the required timing gap has elapsed

 This bit is cleared on a write operation and set once the write completes,
indicating to software that another write or read may be started safely.
Software should poll WDTCTL for WRC=1 prior to accessing another register.
INITIALIZATION AND CONFIGURATION

The Watchdog Timer is configured using the following sequence:

1. Load the WDTLOAD register with the desired timer load value.
2. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
3. If the Watchdog is configured to trigger system resets, set the RESEN bit
in the WDTCTL register.
4. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
5. Set the INTEN bit in the WDTCTL register to enable the Watchdog, enable
interrupts, and lock the control register.
REGISTER MAP
THANK YOU !!