ECE555

Lecture 8/9

Nam Sung Kim

University of Wisconsin – Madison
Dept. of Electrical & Computer Engineering

ECE 555 Digital Circuits & Components 1

 Outline
 Adder
• Carry Ripple

• Manchester Carry

• Carry Bypass (or Skip)

• Carry Select

• Paralle Prefix
 Brent-Kung
 Kogge-Stone
• Delay and Power Comparisons

ECE 555 Digital Circuits & Components 2

 Single-Bit Addition
A B A B
Half Adder Full Adder
S Cout S Cout C

Cout  Cout  S
S

A B Cout S A B C Cout S
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

ECE 555 Digital Circuits & Components 3

 Single-Bit Addition
A B A B
Half Adder Full Adder
S  A B Cout S  A B C Cout C

Cout  AB Cout  MAJ ( A, B, C ) S

S

A B Cout S A B C Cout S
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

ECE 555 Digital Circuits & Components 4

 PGK
 For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C
G=
• Propagate: Cout = C
P=
• Kill: Cout = 0 independent of C
K=

ECE 555 Digital Circuits & Components 5

 PGK
 For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C
G=A•B
• Propagate: Cout = C
P=AB
• Kill: Cout = 0 independent of C
 K = ~A • ~B
• Co(G,P) = G+PCi
• S(G,P) = P  Ci

ECE 555 Digital Circuits & Components 6

 Full Adder Design I
 Brute force implementation from eqns
• S=ABCi+ABCi+ABCi+ABCi = Ci (AB+AB)+Ci (AB+AB)
• Co=AB+BCi+ACi=(AB+BCi+Aci)

A A B B C C

A A

B B
A
B S B
C C C
A B B
S
A C C C A
MAJ

B Cout
Cout
C B
B B C A
A B B
A A

ECE 555 Digital Circuits & Components 7

 Full Adder Design II
 Factor S in terms of Co
• S = ABCi + (A + B + Ci)(~Co)

 Critical path is usually Ci to Co in ripple adder

B 6
A 8 B 8 B 8 A 4 B 4 Ci 4
A 6

8 A 8 !Co 4 Ci 6 !S
Ci
4 A 4 2 Ci 3

A 3
A 4 B 4 B 4 A 2 B 2 Ci 2
B 3
Co S

ECE 555 Digital Circuits & Components 8

 Full Adder Design III
!P Identical Delays for Carry
B !B and Sum
Cin

B P
P

P !Cout S
A A Cin Cin
P

!B !P
A

!P Sum generation
P !P

Carry generation
Signal set-up
ECE 555 Digital Circuits & Components 9
 Carry-Ripple Adder
 Simplest design: cascade full adders
• Critical path goes from Ci to Co
• Design full adder to have fast carry delay

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1
S4 S3 S2 S1
• Worst case delay linear with the number of bits
 td = O(N)
 tadder = (N-1)tcarry + tsum

ECE 555 Digital Circuits & Components 10

 Inversion Property

A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A B  Ci 

C o  A B C i  = Co  A B  Ci 

ECE 555 Digital Circuits & Components 11

 Mirror Adder
 Critical path passes through majority gate
• Built from minority + inverter
• Eliminate inverter and use inverting full adder

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1

S4 S3 S2 S1

ECE 555 Digital Circuits & Components 12

 Mirror Adder Cell

B 6
A 8 B 8 B 8 A 4 B 4 Ci 4
A 6

8 A 8 !Co 4 Ci 6 !S
Ci
4 A 4 2 Ci 3

A 3
A 4 B 4 B 4 A 2 B 2 Ci 2
B 3

ECE 555 Digital Circuits & Components 13

 Fast Carry Chain Design
 The key to fast addition is a low latency carry
network
 What matters is whether in a given position a carry
is
• generated Gi = Ai & Bi = AiBi
• propagated Pi = Ai  Bi (sometimes use Ai | Bi)
• annihilated (killed) Ki = !Ai & !Bi

 Giving a carry recurrence of

C1 = Ci+1 = Gi | PiCi
C2 =
C3 =
C4 =

ECE 555 Digital Circuits & Components 14

 Fast Carry Chain Design
 The key to fast addition is a low latency carry
network
 What matters is whether in a given position a carry
is
• generated Gi = Ai & Bi = AiBi
• propagated Pi = Ai  Bi (sometimes use Ai | Bi)
• annihilated (killed) Ki = !Ai & !Bi

 Giving a carry recurrence of

C1 = G0 | P0C0 Ci+1 = Gi | PiCi
C2 = G1 | P1G0 | P1P0 C0
C3 = G2 | P2G1 | P2P1G0 | P2P1P0 C0
C4 = G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 C0

ECE 555 Digital Circuits & Components 15

 Manchester Carry Chain
 Switches controlled by Gi and Pi

!Ci+1 !Ci
Gi
Pi
clk

 Total delay of
• time to form the switch control signals Gi and Pi
• setup time for the switches
ECE 555 Digital Circuits & Components 16
 4-bit Sliced MCC Adder
A3 B3 A2 B2 A1 B1 A0 B0
clk

&  &  &  & 

G P G P G P G P

!C4 !C0

!C3 !C2 !C1

   

S3 S2 S1 S0

ECE 555 Digital Circuits & Components 17

 Domino Manchester Carry Chain Circuit

3 3 3 3 3 clk
P3 P2 P1 P0

Ci,4 1 2 3 4

1 G3 2 G2 3 G1 4 G0 5 Ci,0

2 3 4 5 6 clk

!(G0 | P0 Ci,0)
!(G2 | P2G1 | P2P1G0 | P2P1P0 Ci,0)

!(G1 | P1G0 | P1P0 Ci,0)

!(G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 Ci,0)

ECE 555 Digital Circuits & Components 18

Carry-Skip (Carry-Bypass) Adder
A3 B3 A2 B2 A1 B1 A0 B0

Co,3
FA FA FA FA Ci,0
Co,3
S3 S2 S1 S0

BP = P0 P1 P2 P3 “Block Propagate”

If (P0 & P1 & P2 & P3 = 1) then Co,3 = Ci,0 otherwise the

block itself kills or generates the carry internally

ECE 555 Digital Circuits & Components 19

Carry-Skip Chain Implementation
block carry-out
carry-
out BP
block carry-in

P3 P2 P1 P0

!Cout Cin
G3 G2 G1 G0

BP

ECE 555 Digital Circuits & Components 20

 4-bit Block Carry-Skip Adder
bits 12 to 15 bits 8 to 11 bits 4 to 7 bits 0 to 3

Setup Setup Setup Setup

Carry Carry Carry Carry

Propagation Propagation Propagation Propagation
Ci,0

Sum Sum Sum Sum

Worst-case delay  carry from bit 0 to bit 15 = carry generated

in bit 0, ripples through bits 1, 2, and 3, skips the middle two
groups (B is the group size in bits), ripples in the last group from
bit 12 to bit 15

Tadd = tsetup + B tcarry + ((N/B) -1) tskip +(B -1)tcarry + tsum

ECE 555 Digital Circuits & Components 21
 Carry Select Adder

4-b Setup
Precompute the carry P’s G’s
out of each block for
both carry_in = 0 and “0” carry propagation 0
carry_in = 1 (can be
done for all blocks in
“1” carry propagation 1
parallel) and then select
the correct one
Cout multiplexer Cin
C’s
Sum generation

S’s
ECE 555 Digital Circuits & Components 22
Carry Select Adder: Critical Path
bits 12 to 15 bits 8 to 1 bits 4 to 7 bits 0 to 3
A’s B’s A’s B’s A’s B’s A’s B’s

Setup Setup Setup Setup

P’s G’s P’s G’s P’s G’s P’s G’s

“0” carry “0” carry “0” carry “0” carry 0

“1” carry “1” carry “1” carry “1” carry 1

mux mux mux mux

Cout Cin
C’s C’s C’s C’s

Sum gen Sum gen Sum gen Sum gen

S’s S’s S’s S’s

ECE 555 Digital Circuits & Components 23

Carry Select Adder: Critical Path
bits 12 to 15 bits 8 to 1 bits 4 to 7 bits 0 to 3
A’s B’s A’s B’s A’s B’s A’s B’s

1
Setup Setup Setup Setup
P’s G’s P’s G’s P’s G’s P’s G’s

“0” carry “0” carry “0” carry “0” carry 0

+4

“1” carry “1” carry “1” carry “1” carry 1

+1
mux +1
mux +1
mux +1
mux
Cout Cin
C’s C’s C’s C’s

Sum gen Sum gen Sum gen Sum gen

S’s S’s S’s S’s

Tadd = tsetup + B tcarry + N/B tmux + tsum
ECE 555 Digital Circuits & Components 24
 Square Root Carry Select Adder
bits 14 to 19 bits 9 to 13 bits 5 to 8 bits 2 to 4 bits 0 to 1
A’s B’s A’s B’s A’s B’s A’s B’s A’s B’s

Setup Setup Setup Setup Setup

P’s G’s P’s G’s P’s G’s P’s G’s P’sG’s

“0” carry “0” carry “0” carry “0” carry “0” carry 0

“1” carry “1” carry “1” carry “1” carry “1” carry 1

Cout mux mux mux mux mux

C
C’s C’s C’s C’s C’s in

Sum gen Sum gen Sum gen Sum gen Sum gen

S’s S’s S’s S’s

S’s

ECE 555 Digital Circuits & Components 25

 Square Root Carry Select Adder
bits 14 to 19 bits 9 to 13 bits 5 to 8 bits 2 to 4 bits 0 to 1
A’s B’s A’s B’s A’s B’s A’s B’s A’s B’s

Setup Setup
1
Setup
Setup Setup
P’s G’s P’s G’s P’s G’s P’s G’s P’sG’s

“0” carry “0” carry “0” carry “0” carry “0” carry 0
+6 +5 +4 +3 +2

“1” carry “1” carry “1” carry “1” carry “1” carry 1

+1 +1 +1 +1 +1
mux
Cout mux mux mux mux C
C’s C’s C’s C’s C’s in

Sum+1gen Sum gen Sum gen Sum gen Sum gen

S’s S’s S’s S’s

S’s

Tadd = tsetup + 2 tcarry + √N tmux + tsum

ECE 555 Digital Circuits & Components 26
Adder Delays - Comparison
50

40 Ripple adder
tp (in unit delays)

30

Linear select
20

10
Square root select

0
0 20 40 60
N

ECE 555 Digital Circuits & Components 27

 Parallel Prefix Adders (PPAs)
 Define carry operator on (G,P) signal pairs
(G’’,P’’) (G’,P’)

where
G = G’’  P’’G’
(G,P)
P = P’’P’
• is associative, i.e.,
[(g’’’,p’’’) (g’’,p’’)] (g’,p’) = (g’’’,p’’’) [(g’’,p’’)
(g’,p’)]

ECE 555 Digital Circuits & Components 28

 Parallel Prefix Adders (PPAs)
Black cell Gray cell Buffer
i:k k-1:j i:k k-1:j i:j

i:j i:j i:j

Gi:k Gi:k
Gi:j Gi:j
Pi:k Pi:k Gi:j Gi:j
Gk-1:j Gk-1:j
Pi:j Pi:j
Pi:j
Pk-1:j

(Gi:j,Pi:j) = (Gi:k+Pi:k∙Gk-1:j, Pi:k∙Pk-1:j)

ECE 555 Digital Circuits & Components 29

Parallel Prefix Adders (PPAs)
Co,0 = G0+P0Ci,0

Co,1 = G1+P1Co,0 = G1 +P1(G0+P0Ci,0)

= G1 +P1G0+P1P0Ci,0
= [G1+ P1G0]+[P1P0 ]Ci,0 = G1:0+P1:0 Ci,0

Co,2 = G2 +P2Co,1

Co,3 = G3 +P3Co,2 = G3 +P3(G2 +P2Co,1)

= G3 +P3G2 +P3P2Co,1)
= [G3 +P3G2 ]+ [P3P2]Co,1
= G3:2+P3:2 Co,1
= G3:2+P3:2 (G1:0+P1:0 Ci,0)
= [G +P G ECE
]+[P P Circuits
555 Digital ]C ) &=Components
G +P C 30
 PPA General Structure
 Given P and G terms for each bit position, computing all the
carries is equal to finding all the prefixes in parallel
(G0,P0) ■ (G1,P1) ■ (G2,P2) ■ … ■ (GN-2,PN-2) ■ (GN-1,PN-1)
 Since is associative, we can group them in any order
• but note that it is not commutative

Pi, Gi logic (1 unit delay)  Measures to consider

• number of cells
• tree cell depth (time)
Ci parallel prefix logic tree • tree cell area
(1 unit delay per level) • cell fan-in and fan-out
• max wiring length
• wiring congestion
Si logic (1 unit delay) • delay path variation (glitching)

ECE 555 Digital Circuits & Components 31

 Brent-Kung PPA
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0
p15 p14 p13 P12 p11 P10 p9 P8 P7 P6 P5 P4 P3 p2 P1 P0 Cin

T = log2N
Parallel Prefix Computation

A = 2log2N
T = log2N - 2
C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1
A = N/2

ECE 555 Digital Circuits & Components 32

 Brent-Kung PPA
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0
p15 p14 p13 P12 p11 P10 p9 P8 P7 P6 P5 P4 P3 p2 P1 P0 Cin

T = log2N
Parallel Prefix Computation

A = 2log2N
T = log2N - 2
C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1
A = N/2

ECE 555 Digital Circuits & Components 33

 Kogge-Stone PPF Adder
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Cin
Parallel Prefix Computation

A = log2N
T = log2N
C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1
A=N
Tadd = tsetup + log2N t + tsum
ECE 555 Digital Circuits & Components 34
 More Adder Comparisons
70

60

50

40 RCA
CSkA
30 KS PPA
20

10

0
8 bits 16 bits 32 bits 48 bits 64 bits

ECE 555 Digital Circuits & Components 35

 Adder Speed Comparisons
70

60

50 RCA
MCC
40 CCSkA
CCSlA
30 B&K

20

10
16 bits 32 bits 64 bits

ECE 555 Digital Circuits & Components 36

Adder Average Power Comparisons
35

30

25
RCA
20 MCC
CCSkA
15 CCSlA
10 B&K

0
16 bits 32 bits 64 bits

ECE 555 Digital Circuits & Components 37

 PDP of Adder Comparisons
100

80
RCA
60 MCCA
CCSkA
40 CCSlA
BKA
20

0
8 bits 16 bits 32 bits 48 bits 64 bits

ECE 555 Digital Circuits & Components 38