Differential Amplifiers:

Implementation on ICs
Replacing RSS and RD with
current-sources and active loads

F. Najmabadi, ECE102, Fall 2012 (1/29)

 Resistor Rss provides
source degeneration for a stable bias
Bias (Common Mode circuit )

ID ID
ID

ID ID ID

2ID

 In discrete circuits, bias is similar to that of a CS amplifier (source degeneration

with a source resistor).
 However RSS does not affect the differential gain and , in fact, should be large
to improve CMRR (no need for a by-pass capacitor!)

F. Najmabadi, ECE102, Fall 2012 (2/29)

 Differential amplifier with current source active load
Q1 and Q2 are identical &VG2 = VG1

Q3 and Q4 are identical

o Q3/Q4 act active load/
current source (similar to a
CS amplifier).

Q5 is necessary
o For signals, Q5 provides RSS = ro5 necessary for reducing common-mode gain (a
large RSS = ro5 can be obtained without significant voltage drop across Q5).
o Parameters of Q5 (i.e., W/L, VG) should be chosen such that ID3 = ID4 = 0.5 ID5 .
o Q5 eases the necessary precision in biasing Q1 and Q2 gates.
F. Najmabadi, ECE102, Fall 2012 (3/29)
 Differential amplifier with
current source active load – Bias
 Q1 and Q2 are identical & VG2 = VG1
 Q3 and Q4 are identical
 Parameters of Q5 (i.e., W/L, VG) are chosen such
that ID3 = ID4 = 0.5 ID5

VGS 1 = VGS 2 ⇒ VOV 1 = VOV 2

I D1 = I D 2 = I D 3 = I D 4 = 0.5 I D 5

Ignoring channel-width modulation:*

1. ID1 = ID3 = 0.5 ID5 sets VOV1 and VGS1
2. VS1 = VGS1 −VG1
3. VD5 = VS1
4. VDS5 = VS1 +VSS
5. We need to include channel-width modulation to
find VDS1 and VDS3
6. Precise biasing of Q1 and Q2 are not necessary to
get correct ID1 (it only affects VDS1 and VDS3 )*

* Similar results are obtained if we do not ignore channel-width modulation:

F. Najmabadi, ECE102, Fall 2012 (4/29) VS =VD5 will adjust to get the correct VGS1 and VOV1 (See problem set)
 Differential amplifier with
current source active load – Signal analysis

ro3 = ro4

ro5

F. Najmabadi, ECE102, Fall 2012 (5/29)

 Differential amplifier with
current source active load – Signal analysis
Differential Mode
vo1,d = − g m1 (ro1 || ro3 ) (−0.5vd ) = 0.5 g m1 (ro1 || ro3 )vd
vo 2,d = −vo1 = −0.5 g m1 (ro1 || ro3 )vd

Common Mode

vo1,c g m1ro 3
=−
vc 1 + 2 g m1ro 5 + ro 3 / ro1
vo1,c = vo 2,c

F. Najmabadi, ECE102, Fall 2012 (6/29)

 Cascode differential amplifier

Cascode active load

Cascode amplifier

No reason to put a cascode

current source here.

Bias analysis is similar to the case of differential

amplifier with current-source active load.
F. Najmabadi, ECE102, Fall 2012 (7/29)
 Cascode differential amplifier – Signal analysis

Small
signal

F. Najmabadi, ECE102, Fall 2012 (8/29)

 Cascode differential amplifier – Signal analysis
Differential Mode

From Lecture Set 6:

g m1 g m 3 g m 5 ro1ro 3 ro 5 ro 7
vo1,d ≈ − × (−0.5vd )
g m 3 ro1ro 3 + g m 5 ro 5 ro 7
= − g m1 ( g m 3 ro3 ro1 || g m 5 ro5 ro7 )(−0.5vd )
vo 2,d = −vo1,d

F. Najmabadi, ECE102, Fall 2012 (9/29)

 Cascode differential amplifier – Signal analysis
Common Mode

For gm ro >> 1*
g m 5 ro 5 ro 7
vo 2,c = vo1,c ≈ − × vc
2ro 9

F. Najmabadi, ECE102, Fall 2012 (10/29) * Derive the expression for vo1,c
 Differential Amplifiers –
Output Configurations

Typical implementation of differential amplifier circuits

Two outputs Single ended output

F. Najmabadi, ECE102, Fall 2012 (11/29)

 Output Configurations of Differential Amplifiers
Differential Output

Single-ended Output Two Separate Outputs

F. Najmabadi, ECE102, Fall 2012 (12/29)

Differential Amplifiers with Differential Output
Differential Mode

Differential Output

Common Mode

Not used often because the load floats

(i.e., not attached to the ground

F. Najmabadi, ECE102, Fall 2012 (13/29)

Differential Amplifiers with Differential Output
Differential Mode
vo1,d = − g m (r o ||R D || RL /2)(−0.5vd )
vo 2,d = −vo1,d
vod = vo 2,d − vo1,d = −2vo1,d = − g m (r o ||R D || RL /2)vd
Differential Output
vod
Ad = = − g m (r o ||R D || RL /2)
vd

Common Mode vo1,c gm R D

=−
vc 1 + 2 g m R SS + R D / ro
vo 2,c = vo1,c
voc = vo 2,c − vo1,c = 0
voc
Ac = =0
vo = Ac ⋅ vc + Ad ⋅ vd vc

| Ad |
CMRR = =∞
| Ac |
F. Najmabadi, ECE102, Fall 2012 (14/29)
 Differential Amplifiers with Two Outputs
Differential Mode

Two Separate Outputs (RL1 ≈ RL2 = RL)

(i.e., input to another difference amplifier)

Common Mode

Note: To use half circuit, (RL1 ≈ RL2) or

RL should be large enough so that
symmetry is preserved (i.e. RL1,2 >> Ro)

F. Najmabadi, ECE102, Fall 2012 (15/29)

 Differential Amplifiers with Two Outputs
Differential Mode

vo1,d
= − g m (r o ||R D || RL1 )
− 0.5vd
vo 2,d
= − g m (r o ||R D || RL 2 )
+ 0.5vd
Note: Each output has its own
differential- and common-mode
gains: v v
Common Mode A1d = o1,d , A1c = o1,c
vd vc
vo1 = A1c ⋅ vc + A1d ⋅ vd

vo1,c g m ( R D ||R L1 )
=−
vc 1 + 2 g m R SS + ( R D ||R L1 ) / ro
vo 2,c g m ( R D ||R L 2 )
=−
vc 1 + 2 g m R SS + ( R D ||R L 2 ) / ro

F. Najmabadi, ECE102, Fall 2012 (16/29)

 Typical implementation of differential
amplifiers with two outputs

Amplifier Stage A Amplifier Stage B

vo 2, A = vi 2, B

vo1, A = vi1, B

CS Amp:
RL = ∞ for Stage A

F. Najmabadi, ECE102, Fall 2012 (17/29)

 Differential Amplifiers with
Single-ended Output
Differential Mode

Single-ended Output

Common Mode

To use half circuit, RL should be

large enough such that symmetry is
preserved (i.e. RL >> Ro = RD||ro)

F. Najmabadi, ECE102, Fall 2012 (18/29)

 Differential Amplifiers with
Single-ended Output
Differential Mode
vo = Ac ⋅ vc + Ad ⋅ vd
vo 2
= − g m (ro ||R D ||R L )
0.5vd
Single-ended Output
vod = vo 2 = −0.5 g m (ro ||R D ||R L ) vd
vod
Ad = = −0.5 g m (ro ||R D ||R L )
vd

Common Mode

voc g m ( R D || RL )
Ac = =−
vc 1 + 2 g m R SS +( R D || RL ) / ro

To use half circuit, RL Should be

large so that symmetry is preserved
(i.e. RL >> Ro = RD||ro) Note: Ac ≠ 0 which means
CMMR is NOT infinite.
F. Najmabadi, ECE102, Fall 2012 (19/29)
 An implementation of differential amplifiers
with an output (coupled to a CS amplifier)
Differential Amplifier
with a single output CS stage

F. Najmabadi, ECE102, Fall 2012 (20/29)

 Active load for a single-ended output

Works fine but require biasing of
Q3 and Q4 (i.e., VG3)
F. Najmabadi, ECE102, Fall 2012 (21/29)
“Popular” active load for single-ended output
 Q3/Q4 are NOT current sources and do
not require biasing (i.e., VG3)
 Gets a similar gain and CMRR
 But, circuit is NOT symmetric (half-circuit
does not work!)
 Active load for a single-ended output:
Small signal equivalent
Small Signal

Note ro4 = ro3 and gm4 = gm3

Diode-connected
transistor

F. Najmabadi, ECE102, Fall 2012 (22/29)

 Small-signal analysis of single-ended output

Small Signal

Note ro4 = ro3 and gm4 = gm3

Circuit is NOT symmetric
ro2 = ro1 and gm2 = gm1
CANNOT use “half-circuit”
F. Najmabadi, ECE102, Fall 2012 (23/29)
 Small-signal analysis of single-ended output –
Differential Gain (1)

ro4 = ro3 and gm4 = gm3

ro2 = ro1 and gm2 = gm1
vgs1 = − 0.5vd − v5
vgs2 = + 0.5vd − v5

v g 3 − v5
Node vg3 g m 3v g 3 + g m1 (−0.5vd − v5 ) + =0
ro1
vo v −v
Node vo g m 3v g 3 + + g m1 (+0.5vd − v5 ) + o 5 = 0
ro 3 ro1
v5 v5 − v g 3 v5 − vo
Node v5 + + − g m1 (−0.5vd − v5 ) − g m1 (+0.5vd − v5 ) = 0
ro 5 ro1 ro1
F. Najmabadi, ECE102, Fall 2012 (24/29)
 Small-signal analysis of single-ended output –
Differential Gain (2)
Rearranging terms:

 1   1 
vg 3  g m 3 +  + v5  − g m1 −  = +0.5 g m1vd
 ro1   ro1 
 1   1 1 
v g 3 ( g m 3 ) + v5  − g m1 −  + vo  +  = −0.5 g m1vd
  
 ro1   ro 3 ro1 
 1   2 1   1 
v g 3  −  + v5  + 2 g m1 + +  + vo  −  = 0
 ro1   ro1 ro 5   ro1 

Dropping 1/ro terms compared with gm

v g 3 ( g m 3 ) + v5 (− g m1 ) = +0.5 g m1vd
Dropping v5 /ro5 term implies
 1 1 
v g 3 ( g m 3 ) + v5 (− g m1 ) + vo  +  = −0.5 g m1vd that very little current flows into
 ro 3 ro1  ro5 (can remove ro5 from the
 1   1  circuit as done in the textbook)
v g 3  −  + v5 (+ 2 g m1 ) + vo  −  = 0
 ro1   ro1 
F. Najmabadi, ECE102, Fall 2012 (25/29)
 Small-signal analysis of single-ended output –
Differential Gain (3)
v g 3 ( g m 3 ) + v5 (− g m1 ) = +0.5 g m1vd
 1 1 
v g 3 ( g m 3 ) + v5 (− g m1 ) + vo  +  = −0.5 g m1vd
 ro 3 ro1 
 1   1 
v g 3  −  + v5 (+ 2 g m1 ) + vo  −  = 0
 ro1   ro1 
Subtracting second equation from the first*:
vo
= − g m1vd ⇒ vo = − g m1 (ro1 || ro 3 )vd ⇒ Ad = − g m1 (ro1 || ro 3 )
ro1 || ro 3

Adding all three equations give: Note: vg3 << vo

vo vo
2 g m 3v g 3 + = 0 ⇒ vg 3 = −
ro 3 2 g m 3 ro 3

vg 3 = +
g m1 (ro1 || ro 3 )
vd ≈
g m1
vd Textbook Eq. 7.1.40
2 g m 3 ro 3 4 g m 3 ro is incorrect
* This is sloppy math as if subtract 2nd equation from first before dropping ro terms, a vg3 term
appears in the above equation. Fortunately, as vg3 << vo, ignoring vg3 term is justified
F. Najmabadi, ECE102, Fall 2012 (26/29)
 Small-signal analysis of single-ended output –
Common-mode Gain (1)

ro4 = ro3 and gm4 = gm3

ro2 = ro1 and gm2 = gm1
vgs1 = − 0.5vd − v5
vgs2 = + 0.5vd − v5

vg 3 − v5
Node vg3 g m 3vg 3 + g m1 (vc − v5 ) + =0
ro1
vo v −v
Node vo g m 3v g 3 + + g m1 (vc − v5 ) + o 5 = 0
ro 3 ro1

Node v5 v5 v5 − vg 3 v5 − vo
+ + − g m1 (vc − v5 ) − g m1 (vc − v5 ) = 0
ro 5 ro1 ro1
F. Najmabadi, ECE102, Fall 2012 (27/29)
 Small-signal analysis of single-ended output –
Common-mode Gain (2)
vg 3 − v5
g m 3vg 3 + g m1 (vc − v5 ) + =0
ro1
vo v −v
g m 3v g 3 + + g m1 (vc − v5 ) + o 5 = 0
ro 3 ro1
v5 v5 − vg 3 v5 − vo
+ + − g m1 (vc − v5 ) − g m1 (vc − v5 ) = 0
ro 5 ro1 ro1

Subtracting second equation from the first and dropping 1/ro terms compared with gm
vo
=0 ⇒ Ac = 0 ⇒ CMRR = ∞
ro1 || ro 3

Solving equations without dropping 1/ro terms compared with gm

1 1
vo = vc ⇒ Ac = ⇒ CMRR = 2 g m 3 ro 5 g m1 (ro1 || ro 3 )
2 g m 3 ro 5 2 g m 3 ro 5

F. Najmabadi, ECE102, Fall 2012 (28/29)

 Small-signal analysis of single-ended output –
Output Resistance

Attach a source vx to the

output and calculate ix)

Subtracting second equation

vg 3 − v5 from the first and dropping
Node vg3 g m 3vg 3 + g m1 (−v5 ) + =0 1/ro terms compared with gm
ro1
vx
vx v −v = ix
Node vx g m 3v g 3 + + g m1 (−v5 ) + x 5 = ix ro1 || ro 3
ro 3 ro1
vx
v5 v5 − v g 3 v5 − v x Ro = = ro1 || ro 3
Node v5 + + − g m1 (−v5 ) − g m1 (−v5 ) = 0 ix
ro 5 ro1 ro1
F. Najmabadi, ECE102, Fall 2012 (29/29)