Half Adder (1-bit)

A B S(um) C(arry)

0 0 0 0
A B
0 1 1 0
1 0 1 0
S 1 1 0 1
Half
Adder
C

Half Adder (1-bit)

A B S(um) C(arry)

0 0 0 0

A 0 1 1 0
Sum 1 0 1 0
B
1 1 0 1

Carry

S  AB  AB  A  B
C  AB

1
Full Adder
Cin A B S(um) Cout
0 0 0 0 0
A B 0 0 1 1 0
0 1 0 1 0

S 0 1 1 0 1
Carry In Full 1 0 0 1 0
(Cin) Adder 1 0 1 0 1
Cout
1 1 0 0 1
1 1 1 1 1

Full Adder
Cin A B S(um) Cout
AB
Cin 00 01 11 10 0 0 0 0 0
0 1 0 1 0 0 1 1 0
0
1 0 1 0
0 1 0 1 0
1
0 1 1 0 1
S  Cin A B  Cin AB  CinAB  Cin A B
1 0 0 1 0
 Cin( A B  AB) Cin (AB  A B)
1 0 1 0 1
 Cin( A  B)  Cin (A  B) 1 1 0 0 1
 Cin  A  B 1 1 1 1 1
AB AB
Cin 00 01 11 10 Cin 00 01 11 10

0 0 0 1 0 0 0 0 1 0
Or
1 0 1 1 1 1 0 1 1 1

Cout  CinB  CinA  AB Cout  AB  Cin( AB  A B)  AB  Cin(A  B)

2
Full Adder
S  Cin  A  B
Cout  AB  Cin(A  B)
H.A. H.A.
A

B S

Cin

Cout

Full Adder
S  Cin  A  B
Cout  AB  Cin(A  B)

A S
A S A S
Half Half
Adder Adder
B B C B C Cout

Cin

3
 4-bit Ripple Adder using Full Adder

A3 B3 A2 B2 A1 B1 A0 B0

A B A B A B A B
Carry Full Full Full Full
Cout Cin Cout Cin Cout Cin Cout Cin
Adder Adder Adder Adder

S S S S

S3 S2 S1 S0

A S A
S
B H.A. H.A. B
Cout
C Cin
Full Adder
Half Adder

Full Adder Propagation Delay

A0 B0

Carry Cin

S0

1st Stage Critical Path

= 3 gate delays
= DXOR+DAND+DOR

4
 Full Adder Propagation Delay

A1 B1 A0 B0

Cin

S1 S0

2nd Stage Critical Path 1st Stage Critical Path

= 2 gate delays = 3 gate delays
= DAND+DOR = DXOR+DAND+DOR
(Since 1st Critical path
> DXOR)

Issue of 4-bit Ripple Adder

A3 B3 A2 B2 A1 B1 A0 B0

Carry Cin

S3 S2 S1 S0

Critical Path = DXOR+4*(DAND+DOR) for 4-bit ripple adder (9 gate levels)

For an N-bit ripple adder

Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays

5
Issue of Ripple Adder
• Carry propagation is the main issue in an
N-bit ripple adder
• A faster adder needs to address the serial
propagation of the carry bit
• Let’s re-examine the equation for full
adders

Carry Generate & Propagate

Ci 1  Ai Bi  Ci (Ai  Bi )
g i  A i Bi (generate)
p i  A i  Bi (propagate)

Ci1  g i  pi Ci
C1  g 0  p 0C0
C 2  g1  p1C1  g1  p1g 0  p1p 0C0
C3  g 2  p 2C 2  g 2  p 2g1  p 2 p1g 0  p 2 p1p 0C0
C 4  g 3  p3C3  g 3  p3g 2  p3p 2g1  p3p 2 p1g 0  p3p 2 p1p 0C0
Note that all the carry’s are only
dependent on input A and B and C

6
 4-bit Carry-Lookahead Adder (CLA)

C4 Carry Lookahead Logic C0

C3 C2 C1

g3 p3 g2 p2 g1 p1 g0 p0

A3 B3 A2 B2 A1 B1 A0 B0
S3 S2 S1 S0

Si  Ci  Ai  Bi g i  A i Bi (generate)
p i  A i  Bi (propagate)

Inefficient Implementation of Carry Lookahead Logic

C0

C4

g3 p3 C3 g2 p2 C2 g1 p1 C1 g0 p0

C1  g 0  p 0C0 S3 A3 B3 S2 A2 B2 S1 A1 B1 S0 A0 B0
C 2  g 1  p1C1  g1  p1g 0  p1p 0C0
C 3  g 2 Reuse
p 2C 2  g 2some
 p 2 g1  pgate output
2p 1g 0  p 2p 1p 0C 0
results 
C4  g 3 Little
p 3C 3  gImprovement
3  p 3 g 2  p 3p 2 g 1  p 3p 2p 1g 0  p 3p 2p 1p 0C 0

Carry Delay is 4*DAND + 2*DOR for Carry C4

7
 Implementation of Carry Lookahead Logic

Carry Lookahead Logic

C0
C4

g3 p3 C3 g2 p2 C2 g1 p1 C1 g0 p0

S3 A3 B3 S2 A2 B2 S1 A1 B1 S0 A0 B0
C1  g 0  p 0C0
C 2  g 1  p1C1  g1  p1g 0  p1p 0C0 Only 3 Gate Delay for each Carry Ci
= DAND + 2*DOR
C 3  g 2  p 2C 2  g 2  p 2 g1  p 2p1g 0  p 2p1p 0C0
C4  g 3  p 3C 3  g 3  p 3 g 2  p 3p 2g 1  p 3p 2p1g 0  p 3p 2p1p 0C0 4 Gate Delay for each Sum Si
= DAND + 2*DOR + DXOR

Cascading CLA
• Similar to ripple adder, but different latency
A[15:12] B[15:12] A[11:8] B[11:8] A[7:4] B[7:4] A[3:0] B[3:0]
4 4 4 4 4 4 4 4
A B A B A B A B

CLA CLA CLA CLA

Cout Cin Cout Cin Cout Cin Cout Cin

S S S S
4 4 4 4
S[15:12] S[11:8] S[7:4] S[3:0]

Delay of each stage

is 3 gate levels instead
of 9 of ripple adders

8
 Subtractor Design

B3 B2 B1 B0
Subtract

A3 A2 A1 A0

A B A B A B A B
C Full Full Full Full
Cout Cin Cout Cin Cout Cin Cout Cin
Adder Adder Adder Adder

S S S S

S3 S2 S1 S0

• A – B = A + (-B)
– Take 2’s complement of B
– Perform addition of A and 2’s complement of B

Overflow/Underflow for Signed Arithmetic

8-bit Signed number addition 8-bit Signed number addition

01001000 (+72) 10000001 (-127)

00111001 (+57) 11111010 ( -6)
-------------------- --------------------
(+129) (-133)

What is largest What is smallest

positive number negative number
represented by 8-bit? represented by 8-bit?

9
Overflow/Underflow Detection
Cn-1 An-1 Bn-1 Sn-1 Cn OF

0 0 0 0 0
• Examine the MSB bit
• Bottom line:
0 0 1 1 0
– P: positive; N: negative
0 1 0 1 0
– N+N=N
0 1 1 0 1 – P+P=P
1 0 0 1 0 – P+N or N+P always fall
into the range
1 0 1 0 1
• E.g. -128+P cannot be
1 1 0 0 1 smaller than -128 or
bigger than 127
1 1 1 1 1
• Problem lies in
Discarded
– N+N = P
– P+P = N

Overflow/Underflow Detection
Cn-1 An-1 Bn-1 Sn-1 Cn OF

0 0 0 0 0 0

0 0 1 1 0 0
OF  CAB  CAB
0 1 0 1 0 0 or
0 1 1 0 1 1 OF  C n 1  C n
1 0 0 1 0 1

1 0 1 0 1 0

1 1 0 0 1 0

1 1 1 1 1 0
Discarded

10
 Overflow/Underflow Detection
A3 B3 A2 B2 A1 B1 A0 B0
A B A B A B A B
Carry
Full Full Full Full
Cout Cin Cout Cin Cout Cin Cout Cin
Adder Adder Adder Adder
S S S S
Overflow/
Underflow S3 S2 S1 S0

Cn
n-bit Adder/Subtractor
Overflow/
Underflow

Cn-1

Overflow/Underflow Example

8-bit Signed number addition 8-bit Signed number addition

01001000 (+72) 10000001 (-127)

00111001 (+57) 11111010 ( -6)
-------------------- --------------------
(+129) (-133)

Cn-1 = Cn-1 =

Cn = Cn =

11
Parity Circuits

N-bit data

Sender Receiver
Parity bit

• To detect single bit error during transmission

• Parity bit
– Even parity: even number for data+parity
– Odd parity: odd number for data+parity
• Single parity bit
– Cannot detect 2 bit error
– Cannot correct the single bit error

Even Parity Generation

4-bit data

Sender Receiver
Parity bit (P_GEN)
D0

D1 P_GEN

D2

D3

P_GEN = D0  D1  D2  D3

P=1 if odd number of inputs is 1

P=0 if even number of inputs is 1

12
Even Parity Detection
4-bit data

Sender Receiver
Parity bit (P_GEN)
D0
P_RECV
D1
D2

D3

P_RECV = D0  D1  D2  D3
DETECTION = P_GEN  P_RECV Detection
P_GEN
DETECTION=1 if P_GEN P_RECV

Parity Detection Example

4-bit data
0111
Sender Receiver
Parity bit (P_GEN)
1

D3=0

D2=1 P_GEN=1

D1=1

D0=1

13
Parity Detection Example
Error occur during transmission
4-bit data
0101
Sender Receiver
Parity bit (P_GEN) 1
D3=0
P_RECV=0
D2=1
D1=0

D0=1

Detection=1
P_GEN=1

14