MICROCONTROLLERS

LECTURE NOTES no. 8

Lecturer PhD. bioeng. Monica-Claudia Dobrea

Summary

Buses

 CPU’s internal buses

 I/O buses
CPU’s internal buses

CPU’s internal buses

 The rate at which the CPU completes its operations is determined by the bus structure inside
the CPU.
 The cost of the CPU increases with the complexity of the bus structure.
 Three types of bus structures are typically used:
 single-bus,
 two-bus, and
 three-bus architectures.
CPU’s internal buses

Single-bus organization

 Is the simplest of all bus structures.

 At any time, data may be transferred between any two registers or between a register and the ALU.
 The bus must be multiplexed among various data.

 If the ALU requires two operands such as

in response to an ADD instruction, the
data can only be transferred one at a time.
 More, the ALU must have buffer registers
to hold the transferred data.
CPU’s internal buses

Single-bus organization

 It slows down the speed of instruction execution even though data may already be in the CPU registers –
two clock cycles may be required to retrieve the operands into the CPU registers from external memory.
 To execute an instruction such as ADD between two operands already in register, the control logic in a
single-bus structure must follow a three-step sequence. Single-bus architecture
Each step represents a control state.

Therefore, a single-bus architecture

requires a large number of states in the
control logic; hence, more hardware may be
needed to design the control unit.

On the other hand, because all data transfers

take place through the same bus one at a
time, the design effort to build the control
logic is reduced.
CPU’s internal buses

Single-bus organization

This architecture perform the addition operation R0 ← R1 + R2 in three clock cycles as follows:

First clock cycle:

 The contents of R1 are moved to buffer register B1
of the ALU.
Second clock cycle:
 The contents of R2 are moved to buffer register B2
of the ALU.
Third clock cycle:
 The sum generated by the ALU is loaded into R0.
CPU’s internal buses

Two-bus architecture

 All GPRs are connected to both buses (bus A and bus B) to form a two-bus architecture.
 The two operands required by the ALU are, therefore, routed in one clock cycle.
 Instruction execution is faster because the ALU does not have to wait for the second operand, unlike the
single-bus architecture.
 The information on a bus may be from a
GPR or a special-purpose register.
 The special-purpose registers are often
divided into two groups.
• Each group is connected to one of
the buses.
• Data from two special-purpose
registers of the same group cannot
be transferred to the ALU at the
same time.
CPU’s internal buses

Two-bus architecture
 The contents of the PC (program counter) are always transferred to the right input of the ALU because it is
connected to bus A.
Similarly, the contents of the special register MBR (memory buffer register, to hold up data retrieved from
external memory) are always transferred to the left input of the ALU because it is connected to bus B.

This architecture perform the addition operation

R0 ← R1 + R2 in two clock cycles as follows:
First cycle:
 The contents of R1 and R2 are moved to
the inputs of the ALU. The ALU then
generates the sum in the output register.
Second cycle:
 The sum from the output register is
routed to R0.
CPU’s internal buses

Three-bus architecture
 The performance of a two-bus architecture can be improved by adding a third bus (bus C), at the output
of the ALU.

This architecture perform the addition

operation R0← R1 + R2 in one cycle as
follows:
First cycle:
 The contents of R1 and R2 are moved
to the inputs of the ALU via bus A
and bus B, respectively.
 The sum generated by the ALU is
then transferred to R0 via bus C.

The addition of the third bus increases the system

cost and, also, the complexity of the control unit
design.
Standard I/O Buses and Interfaces

The bus is a critical component of a computer:

 Buses are shared components that provide the paths for all parts of the computer to
communicate with each other.
 They can reduce the complexity of communications between computer components.
 They contain conduits for data, “addressing”, and timing/control.
 They need a protocol that all users use.
 They can provide an easy way to evolve a computer system – add components.
 They can be a serious bottleneck if not designed and used appropriately.
 As systems grow, they need to evolve hierarchically.
 They can be parallel or serial.
 They can have data widths larger than the computer word length.
Hierarchical organization of computer buses

The System Bus

The main information that the microprocessor exchanges with the outside world are:
 data (operands and results), instructions,
 addresses,
 control information.
All of these are transmitted as electrical signals (binary encoded) through conductive lines
grouped into the buses.
The assembly of the electrical lines to which the microprocessor, memory and I/O system of a
computer are connected is called: the system bus.
Traditionally, the lines included in the microprocessor external bus are functionally classed into:

 data bus;
 address bus, and
 control bus.
System Bus

The MPU communicates with Memory and I/O using the System Bus:

Address bus
Unidirectional
Memory and I/O Addresses
Data bus
Bidirectional
Transfers Binary Data and Instructions
Control lines
Read and Write timing signals
Hierarchical organization of computer buses

 The bus is a communication channel shared over time by several units connected to the bus
lines.
 Sharing (multiplexing) over time is required, because only one device can transmit bus data
at a time. For this reason, connecting multiple devices to the same bus system may become
inefficient from the point of view of the communication speed on a single shared bus.
 To overcome the overload of the communication channel, and, moreover, to increase its
performance, a hierarchy of several interconnected buses is made.
Hierarchical organization of computer buses

The main reasons for the implementation of several buses, organized as a buses hierarchy, are:
 The more devices are connected to a bus, the greater the physical length of the bus (this can
lead to long delays in digital signal transmission with very high clock frequencies).
 The more devices are connected to a bus, the longer the data transmission delay due to the
waiting times will be.
 The more devices connected to the same bus lines increase the parasitic capacity of each
line, which produces a digital signal integration effect and the possibility that a transmitted
digital signal no longer complies with the HIGH logic level.
 Devices connected to a bus have very different operating speeds (for example, think to the
CPU speed compared to the peripheral equipment).
Hierarchical organization of computer buses

 In modern digital systems, the transfer between CPUs and memory, respectively I/O devices, is
done through hierarchically organized buses, depending on the speed of devices coupled to each
bus.
 There are several organizational variants depending on:
 the type of computer (general or specific applications) and
 the speed differences between devices.

o Most computers use multiple buses, organized as a hierarchy of buses with different operating
speeds.

o A classical structure of multiple busses organized on levels is shown in next figure.

Hierarchical organization of computer buses

 The (1) local bus:

Example of
 connects the cache memory with the processor; hierarchical
organization
 to this some high speed I/O (local) devices of computer
can be connected too. buses

 The cache memory controller interfaces the

cache memory with the processor and also with
the (2) system bus to which the main memory is
connected.
The advantage of this approach is that:
o direct transfer between I/O devices and
memory does not interfere with the work of
the CPU that works directly with the cache;

 I/O devices are connected to the third hierarchical level called (3) extension bus (also called I/O buses). This
one allows to connect a large number and a wide variety of I/O devices to the extension bus (it supports a
wide range of transfer rates) and, at the same time, isolates the processor to-memory traffic from the I/O
traffic.
Hierarchical organization of computer buses

 Classical bus architecture is efficient, but it does not

deal with new I/O devices that are running at higher
speeds.
 New implementations have emerged, introducing a
high-speed intermediate (sometimes called mezza-
nine) bus interfacing through a bridge with the local
processor bus. This high-speed bus can connect high-
speed LAN controllers (such as Fast Ethernet to 100
Mbps, video-graphic controller etc.). In this approach:
 the cache controller is integrated into a bridge,
or a buffer device, which connects to the high-
speed bus;
 the low-speed I/O devices continue to be coupled
to the extension bus, which is, on its turn, Another approach of hierarchical organization of
connected via an interface to the high-speed computer buses
bus.
The advantage of this arrangement: the high-speed I/O devices are integrated closer to the processor and can
work alongside the processor at the same time, in parallel.
Main features of the buses

The main buses characteristics include:

 arbitration approach (allowing data to be
transmitted on the bus lines can be
centralized or decentralized),
 synchronization (if the bus signals are
synchronized with a clock signal, or they are
sent asynchronously and conditioned by
signals previously transmitted) and
 the width of the bus (i.e., the number of
address/data lines).

Another approach of hierarchical organization of

computer buses
Main features of the buses

Arbitration
Arbitration of buses is required in all computers,
even in the single-processor systems.

For example, a peripheral may require data

to be transferred directly to the memory using
the I/O interface and a Direct Memory
Access (DMA) controller.

To carry out the transfer, the DMA controller

will temporarily take over the buses control.

The different methods of buses arbitration can be

Another approach of hierarchical organization of
categorized into two categories: computer buses
 centralized arbitration and
 decentralized arbitration.
Main features of the buses

Arbitration
1) In a centralized arbitration system, there is only one
hardware device, called bus controller (arbitrator)
that allocates time for taking control of the buses.

This arbitration approach can be:

 programmable or
 fixed (according to the priorities assigned to
the various master devices connected to the
bus).
Example: The simplest centralized fixed arbitration
scheme can be conceived using a priority
encoder so that in the case of a request for
control received from two or more devices, Another approach of hierarchical organization of
the one with the highest priority be served. computer buses
Main features of the buses

Arbitration
2) For decentralized priority, as the name suggests:
 there is no central referee anymore;
 each device that can take the control of the buses
contains the logic required to set the priority.

Priorities are fixed and embedded in hardware - by

the way itself of interconnecting modules.

Often, in this bus arbitration approach, linking devices

into a chain of priorities is used (we will present a
description of the chain of priorities later, in the I/O
system lecture).
Another approach of hierarchical organization of
computer buses
Main features of the buses

Synchronization
From the point of view of how information is transferred
on the buses, this can be :
 synchronous or
 asynchronous.

Synchronous buses

• In a synchronous bus, bus operations are synchronized

with reference to a local clock signal.
• The bus clock is generally derived from the computer
system clock; however, often it is slower than the master
clock.
For instance, 66 MHz buses are used in systems with a
processor clock of over 500MHz.
Synchronous buses

• Buses are traditionally slower than processors because

memory access times are typically longer than
processor clock cycles.
• A bus transaction often takes several clock cycles,
although the cycles are collectively referred to by many
as a bus cycle.

 Thanks to synchronization, transfers control is

extremely simple.

 The interface (bridge) blocks between synchronous

buses running at different clock frequencies must
achieve the speed adaptation in such a way that the
transfers between the buses are done correctly and
as quickly as possible.
Synchronous buses

• Buses are traditionally slower than processors because

memory access times are typically longer than
processor clock cycles.
• A bus transaction often takes several clock cycles,
although the cycles are collectively referred to by many
as a bus cycle.

 Thanks to synchronization, transfers control is

extremely simple.

 The interface (bridge) blocks between synchronous

buses running at different clock frequencies must
achieve the speed adaptation in such a way that the
transfers between the buses are done correctly and
as quickly as possible.
Synchronous buses

• Buses are traditionally slower than processors because

memory access times are typically longer than
processor clock cycles.
• A bus transaction often takes several clock cycles,
although the cycles are collectively referred to by many
as a bus cycle.

 Thanks to synchronization, transfers control is

extremely simple.

 The interface (bridge) blocks between synchronous

buses running at different clock frequencies must
achieve the speed adaptation in such a way that the
transfers between the buses are done correctly and
as quickly as possible.
Asynchronous buses

On asynchronous busses:
 the bus has no system clock;
 transfers do not have to be achieved within a fixed
time frame, and
 transfer control is done by means of handshaking
signals interchanged between the correspondents.
Asynchronous buses

On asynchronous busses:
 the asynchronous data transfers between two
independent units require transmission control
signals between the communicating units to indicate
when the data is available;
 even if asynchronous transfers are slower than
synchronous transfers, implementation is often
necessary if the speeds of the two transferring
modules are very different.

 There are high speed differences between the CPU

and some peripherals - in this case we cannot
implement synchronous communication!
 If the distance (bus length) between the two devices is
large, the asynchronous transfer option is the one
indicated.
For example, if the clock signal period is of 10 ns (i.e., it
has a frequency of 100 MHz), and the data is transmitted
at a distance equivalent to 60 m, the signal is received
after 200 ns (20 clock pulses), considering the velocity
equal to the speed of light in vacuum (3x10^8 m/s).
Asynchronous buses

Asynchronous transfer

Let’s note the two units that communicate as "source" and The process is called
"destination" of the data without specifying the two asynchronous data transfer, with
interlocutors (e.g., microprocessor, memory, I/O interface). confirmation ("handshaking").
One of the control signals initiates the data transfer, and the
second confirms the reception of the data.
Asynchronous buses

For example, in an asynchronous read operation:

 The bus master puts the address and control signals on the
bus and then asserts a synchronization signal.
 The synchronization signal from the master prompts the
slave to get synchronized.
 Once the slave has accessed the data, it asserts its own
synchronization signal (the slave's synchronization signal
indicates to the processor that there is valid data on the
bus, and this one reads the data).
 The master, then, deasserts its synchronization signal,
which indicates to the slave that the master has read the
data.
 The slave then deasserts its synchronization signal.
This method of synchronization is referred to as a full
handshake.
Note that there is no clock and that starting and ending of the
data transfer are indicated by special synchronization signals.
Asynchronous buses

In an asynchronous data transfer, the transfer can be initiated:

 by the source (with strobe - marking data to be transmitted), or
 by the destination (by strobe - data request).
In both cases, the interlocutor will respond with a signal indicating that the data was accepted, or
respectively, the data was provided (Ready).
 Asynchronous buses

The sequence of events for the transfer initiated by the data

source is as follows:
 the source places the data on the common data bus;
 the source validates the data via the marking signal
(Strobe);
 the destination confirms that it is ready for transfer;
 the source disables the Strobe signal, which usually
is responsible for storing the data at destination, too;
moreover, after a while it also disables data on the
bus;
 the destination disables the Ready signal.

 One has to note that the source maintains the active strobe signal
until the destination is able to respond with the Ready signal.
 The duration of the active signals may be extended until the slowest of the correspondents can correctly transfer the
data.
Asynchronous buses

The sequence of events for the transfer initiated by the

destination is as follows:
 the destination launches the Strobe signal,
meaning "data request";
 the source responds by putting the data on the
common bus and then by activating the
confirmation signal (Ready);
 the destination reads the data and confirms this by
deactivating the strobe signal;
 the source considers the transfer is complete and
disables the Ready signal.
Main features of the buses

Width of the bus

Regarding the bus width, the size provided in number of bits indicates
the total number of bits that can be transferred in the time unit:
The higher the number of lines, the higher the speed of information
transfer on the bus, but also the cost of implementation.
Bus standards

 A given computer may use more than one bus

standards.

 A typical Pentium computer has both:

 a PCI bus and
 an ISA bus,
thus providing the user with a wide range of
devices to choose from.
Peripheral Component Interconnect (PCI) Bus

First introduced in 1992, the PCI bus is a good example of a system bus that
grew out of the need for standardization.

Some of its features are:

 It supports the functions found on a processor bus but in a standardized
format that is independent of any particular processor.
 Devices connected to the PCI bus appear to the processor as if they were
connected directly to the processor bus. They are assigned addresses in
the memory address space of the processor.

 The PCI follows a sequence of bus standards that were used primarily in
IBM PCs:
 the 8-bit XT bus (whose signals closely mimicked those of Intel’s
80x86 processors);
 the 16-bit ISA bus (used on the PC At computers);
 the extended 32-bit EISA bus;
 other buses developed in the eighties, with similar capabilities: the
Microchannel (used in IBM PCs) and the NuBus (used in
Macintosh PCs).
Peripheral Component Interconnect (PCI) Bus

Some of its features are:

 It was developed as a low-cost bus.

 Its design anticipated a rapidly growing demand for bus
bandwidth to support high-speed disks and graphic and video
devices, as well as the specialized needs of multiprocessor
systems. As a result, the PCI is still popular as an industry standard
even after two decades of existence.
 An important feature that the PCI pioneered is a plug-and-play
capability for connecting I/O devices. To connect a new device, the
user simply connects the device interface board to the bus. The
software takes care of the rest.
Peripheral Component Interconnect (PCI) Bus

The bus supports three independent address spaces:

 memory,
 I/O, and
 configuration.
Note that the system designer may choose to use memory-mapped I/O even
when a separate I/O address space is available – this approach is recommended
by the PCI’s plug-and-play capability.

A 4-bit command that accompanies the address identifies which of the three
spaces is being used in a given data transfer operation.
 Peripheral Component Interconnect (PCI) Bus

 In the signaling convention on the PCI bus one could assume that the master
maintains the address information on the bus until data transfer is completed.
 But, this is not necessary:
 the address is needed only long enough for the slave to be selected;
 the slave can store the address in its internal buffer;
 thus, the address is needed on the bus for one clock cycle only, freeing
the address lines to be used for sending data in subsequent clock
cycles.
The result is a significant cost reduction because the number of wires on a
bus is an important cost factor. This approach in used in the PCI bus.
 At any given time, one device is the bus master:
 it has the right to initiate data transfers by issuing read and write
commands.
 a master is called an initiator in PCI terminology;
 this is either a processor or a DMA controller.
The addressed device that responds to read and write commands is called a
target.
Peripheral Component Interconnect (PCI) Bus

Device Configuration

 When an I/O device is connected to a computer, several actions are

needed to configure both:
 the device and
 the software that communicates with it.
• The PCI simplifies this process by incorporating in each I/O device
interface a small configuration ROM memory that stores
information about that device.
• The configuration ROMs of all devices are accessible in the
configuration address space.
• The PCI initialization software reads these ROMs whenever the
system is powered up or reset. In each case, it determines whether the
device is a keyboard, an Ethernet interface etc. It can further learn
about various device options and characteristics.
• Devices are assigned addresses during the initialization process.
This means that during the bus configuration operation, devices cannot
be accessed based on their address, as they have not yet been assigned
Peripheral Component Interconnect (PCI) Bus

Device Configuration

• The PCI initialization software reads these ROMs whenever the

system is powered up or reset. In each case, it determines whether the
device is a keyboard, an Ethernet interface etc. It can further learn
about various device options and characteristics.
• Devices are assigned addresses during the initialization process.
This means that during the bus configuration operation, devices cannot
be accessed based on their address, as they have not yet been assigned
one. Hence, the configuration address space uses a different
mechanism. Each device has an input signal called Initialization
Device Select, IDSEL#.
 Signals at the CPU interface with the outside world

The signals from the CPU interface with its outside can be functionally grouped in 3 types of buses:
1. address bus;
2. data bus;
3. control bus.

Data Bus
 The width of the data bus is typically a byte
multiple (d = 8, 16, 32, 64 ... bits).
 The d lines of the data bus have both:
 the possibility of bidirectional transmission
of the information (with entering into or
output from the CPU), and
 the possibility of passing into high-
impedance state (HiZ).
Signals at the CPU interface with the outside world

Data Bus

In order to save pins, some microprocessors

multiplexes the data bus lines over time, so
that address information or control
information can be transmitted in the first
machine cycle of each instruction on the data
bus. In this case:
 in the first part of the machine cycle, on
the multiplexed pins there are generated
the address or control signals,
accompanied by an indicator signal on the
control bus that serves to store the
information in processor's external
registers (e.g., Intel 8085 and 80x86 data
bus pins are multiplexed so that address
information can also be transmitted).
Signals at the CPU interface with the outside world

Data Bus
In order to save pins, some microprocessors
multiplexes the data bus lines over time, so
that address information or control
information can be transmitted in the first
machine cycle of each instruction on the data
bus. In this case:
 in the first part of the machine cycle, on
the multiplexed pins there are generated
the address or control signals,
accompanied by an indicator signal on the
control bus that serves to store the
information in processor's external
registers.
 The control signal that controls the storage of the address in an external register is called ALE (Address Latch
Enable). Then, for the rest of the instruction cycle, the data bus lines transfer the data itself or instructions.
 Typically, the width of the data bus is commonly used in the microprocessor name: "32-bit microprocessor"
indicates that its data bus has a 32-bit width.
 Signals at the CPU interface with the outside world

Address Bus
 This bus is a unidirectional bus that
contains address lines transmitting output
signals of the CPU.
 The lines of this bus are used to address
memory.
 The CPU outputs to this external address
bus can switch to High Impedance (HiZ)
state when an external request is received
and in such a case the CPU passes the
control of the buses to another device.

There are three approaches used for getting the

selecting signals based on the address information:
1. linear addressing;
2. fully decoded addressing;
3. a combined addressing - a combination of the first two modes.
Signals at the CPU interface with the outside world

Linear Addressing
 This type of addressing is used only for
small systems where only part of the total
address space is used.
 In such cases, lines of the address bus can
be used together with control signals to
directly select memory blocks.
For example:
 Let's assume we have a
microprocessor whose address bus
width is of 16 bits;
 so, the maximum addressing space is
of 2^16 memory locations (64 k
locations);
 also, let's assume that the computing system uses only 12 k of memory, consisting of 3 memory
blocks of 4k. Each block can be addressed with 12 address bits (2^12 = 4096 = 4 k).
Signals at the CPU interface with the outside world

Linear Addressing
 If we consider the 12 less significant bits
for addressing within blocks,
 the other 4 bits in the address bus can be
used to select memory blocks.
 A variant of this linear selection mode is
shown in next figure, where it was
assumed that there are:
 two blocks of ROM of 4 kB and
 a block of RAM 4k x 8 (formed of
two 4K x 4 bits RAM circuits).
Linear selection uses:
 the bits a14, a13 and a12 of the address
bus, along with the
 Read and Write control signals, and
 bits a11 - a0 are used to address internal memory locations.
The read and write control signals are LOW logical (that's why they have a bar above their name).
Signals at the CPU interface with the outside world

Completely decoded addressing

 In this mode of selecting the memory
circuits:
 all address lines are used for
addressing, so
 the entire available address space is
used.
The more significant bits of the address
are decoded so that selection signals are
generated for all the memory devices used.

Example: the next figure discloses how to

decode and generate selection signals for
a microprocessor, similar to linear
addressing, where a = 16 bits. By full
decoding, 2^16 memory locations can be
addressed.
Signals at the CPU interface with the outside world

Completely decoded addressing (64 K)

Requirements: Build a memory that uses the (64 K)

fully decoded address with the following

(64 K)
parameters:
 256 KB total storage capacity, (64 K)
 64 KB RAM integrated memory
circuits.

Solution: The first thing to do is to calculate the number of required memory circuits:
256 KB : 64 KB = 4

 For each IC of memory, there is a selection signal (CS) which, if activated, permits working with that
memory for reading/writing operation.
 If this input is not active, the memory's input/output data buffer is inactive (HiZ).

Based on this observation, we can galvanically link the data lines with the same name (D0 to D7)
from all IC together (Di, i = 0-7, from all memory blocks give the 8 lines that bind to the 8-bit
data bus).
Signals at the CPU interface with the outside world

Completely decoded addressing

 With the decoder the CPU can select a single IC at a

time, using for this the 2-bit selection address from the
decoder's input.
 All memory circuits are addressed through the same
address lines (16 bits, because 2^16 = 64K).
Signals at the CPU interface with the outside world

Control Bus

 It contains a variety of:

 control and only one-way (input or output from CPU), and
some of which are
 synchronization lines others allow for bi-directional signals.

This is why it is often said that the control bus is bidirectional.

This bus comprises control signals with different functions from one microprocessor to another.
Signals at the CPU interface with the outside world

Control Bus

However, functionally, the control bus lines can be classified into the following general categories:
 control and synchronization signals for data transfers with memory and I/O devices;
 control and synchronization signals of the requests for the buses control;
 control and synchronization signals with external events generating interrupt requests;
 utility signals such as reset, clock, power supply;
 CPU status signals;
 various signals that are specific to both:
 microprocessors types and
 the purpose for which they were designed.
(different signals include, for example, inputs that can be tested through software, inputs for the CPU's
step-by-step activity command, inputs for signaling errors, inputs/outputs for working in multi-processor
system etc.)
Control Bus

Control signals for data transfer with memory and I/O devices

Role: to control and synchronize transfers on the data bus.

 The sense of the information transfer on the data bus is controlled by signals indicating a read or a write
operation (the meaning of both operations is regarded from the point of view of the CPU).
 In general, the control signals are active at the LOW level, so that the HIGH level corresponds to the
inactive state of the signal.

 (ReaD) signal is indicating that a read operation is performed by the CPU. Some microprocessors
(e.g., the Motorola
Typically, the back edge of the READ signal (the rising edge) is used by the CPU
MC68000 micropro-
to actually read the data loaded on the data bus by the memory or by an I/O
cessor) have one single
device.
output signal ( ),
 (WRite) signal is indicating that a write operation is performed by the CPU. which fulfills both
Typically, the back edge of the WRITE signal is used by the device addressed and functions, for level "1"
selected for the write cycle, to store the data in its own register. doing a reading opera-
tion, and for level "0"
a writing.
Control Bus

Control signals for data transfer with memory and I/O devices

Transfers between the CPU and a slow interlocutor device (memory or port) are usually asynchronous in
order that the CPU can work both:
 at full speed with the fast devices and
 slowly with the slow speed devices.
For this, signals are required for the implementation of the asynchronous communication protocol
(handshake). The minimum set of synchronization signals consists of the followings:

 A signal generated by the CPU indicating to the interlocutor devices that the CPU has
provided (on the address bus) a valid address information (at the location with this address a
writing or a reading will be performed at the next instant).
This signal
will produce a selecting/enabling of
The address
the interlocutor device.
The sense ( ( or ) of the data bus traffic
We will note the address validation with (address Strobe).
Control Bus

Control signals for data transfer with memory and I/O devices

 A signal received by the CPU, indicating that the interlocutor

is ready to make the transfer (i.e., READY signal). This signal
informs the CPU that:
 the device either delivered the data word (in the case of a
read cycle) or
 it is able to receive data (in the case of the write cycle).

If the device cannot respond in a certain amount of time, READY

corresponding to a number of clock pulse periods, it cannot
activate READY and the CPU will enter additional delays until
the transfer become possible: the READY signal is thus used to
synchronize the two interlocutors.

Remember! If READY is inactive (= 0 logic), the CPU will prolong the current machine cycle by
"freezing" all other command signals by adding waiting states (WAIT) until it receives
READY= 1; then, the write machine cycle (or reading) ends.
Control Bus

Control signals for data transfer with memory and I/O devices

 Synchronization with the memory and the input/output devices are similar.
 However, in many computers, by construction, the working memory's speed is known, and
working with the main memory can be regarded as synchronous, not requiring the READY signal.
 In this situation, the transfer takes place strictly within a pre-specified time interval (i.e., as a
number of CPU states).
 In all other cases the transfers are asynchronous, the CPU prolonging the current machine
cycle with a standby until the READY signal becomes active or until another event
(exception or reset) interrupts this machine cycle.
 Generating or not a "READY" signal refers to the asynchronous or synchronous operation
mode.
 In a synchronous working mode, all events take place within a specified time frame.
Control Bus

Control signals for data transfer with memory and I/O devices

Examples of transfer control signals used with different microprocessors are shown in below table.
Control Bus
 Control Bus

The timing diagram of the signals assumes that:

 The GATA input is tested by the microprocessor starting
from the T2 state on each decreasing front of the clock
pulse.
 On the last line of the diagram in next figure the
information was displayed at the outputs of the addressed
memory device. These outputs are coupled to the data bus,
but when the device is not selected, the outputs are in the
high impedance state (HiZ) if the outputs are of the TSL
type. After selecting and addressing the memory device,
the status at the output changes only after the access time
to the memory cells has passed.
Graphic symbols used:
 For the one signal lines the diagram represents the transitions between the logical levels "1" (HIGH) and "0" (LOW).
 In the case of buses, the two parallel lines used with the data buses and addresses bus suggest that the bus information is stable.
 The intersection of the lines indicates the change of information on the bus.
 The hatched areas show that the respective (stable) information is non-significant for the cycle described by the diagram.
Control Bus

Signals to control the requests for getting the buses control

 The problem of requesting/ceding the control of buses can only be taken into discussion into
computational systems that contain several devices that can control the three types of buses.
 These devices that are active on the bus (i.e., master devices that control slave devices) can be
for example:
 other general purpose processors (CPUs),
 processors with specific tasks (e.g., I/O processors), and
 controller circuits that have the possibility to transfer data directly to the main memory
(DMA transfer).
In order for a CPU to be able to decide on the buses control ceding, the arbitrating system for the buses
control must contain at least two types of signals:
 an input signal to the CPU that makes a request for access to the bus control, signal which, from
now on, we will denote by BR (Bus Request);
 an output signal from the CPU that confirms the ceding of the buses control, referred in what
follows by BG (Bus Grant). Following the cession of the busses control, the CPU to which it was
launched BR request passes its outputs to data, addresses and control buses (only part of the control
signals) in high impedance state (HiZ). That's how the control of the buses lines (from the electrical
point of view, of the logical levels) is transferred to whom it was granted.
Control Bus

Signals to control the requests for getting the buses control

 Following the cession of the busses control, the CPU to which it was launched BR request
passes its outputs to data, addresses and control buses (only part of the control signals) in
high impedance state (HiZ).

 In this way, the control of the buses lines (from the electrical point of view, of the logical
levels) is transferred to whom it was granted.

In Table below there are some examples of signals equivalent to the type of signals we have
presented as BR and BG.
Control Bus

Signals to control the requests for getting the buses control

 The CPU endowed with this pair of signals typically probes the BR demand signal at the end of
each machine cycle, and gives up the bus control as soon as possible, except for special cases in
which operations cannot be interrupted (e.g., the operations provided with LOCK prefix to
I8086).
 The maximum delay with which a request for access to bus control is served is, therefore, a
machine cycle.
 In the case of several requests for control buses, priorities analysis is usually done with a
centralized arbitration circuit for bus requests.
Control Bus

Synchronization signals with external events generating interrupt requests

 These signals have the role of synchronizing external events with the CPU.
 The control and sync signals for external interrupt requests are extremely important because:
• they allow a peripheral device to launch a service request signal to the CPU (services
that relate to data transfer, for example) which, in turn,
• determine the CPU to interrupt temporarily the running program,
• to jump to the execution of an interrupt service program, and, after that, finally
• to return to the interrupted program.
Upon receiving an interrupt request, if the CPU accepts interrupting current activity, the
interrupt device will be informed of this. As a result, the device that initiated the interrupt will
generate - for vectorized interruptions only - on the data bus an identifier (interrupt vector)
that will allow routing the execution toward the particular interrupt serving subroutine.
Control Bus

Synchronization signals with external events generating interrupt requests

There are two types of hardware interrupt requests:

 Maskable interrupts whose recognition and serving can be validated or invalidated by setting control
indicators.
 Non-maskable interrupts, the effect of which cannot be blocked/masked, always being recognized.

A minimum set of signals for handling interrupt requests includes:

 At least one entry signal to CPU, representing a request for interruption, through which the
device that launched the request waits for services from the CPU (hereinafter referred to as INT).
Some microprocessors have multiple interrupt request inputs.
 At least one CPU output signal representing acknowledgment of interrupt acceptance (signal
further labeled INTA). In many of the microprocessors, this signal also has the control function
for reading the interrupt vector loaded by the interrupter on the data bus.
Control Bus

Synchronization signals with external events generating interrupt requests

Some examples of INT and INTA signals are shown in table below.
Control Bus

CPU status indicator signals

 These are usually signals, or combinations of output signals, indicating the state of the microprocessor.
 The state of the machine is important for different additional circuits connected to the microprocessor interface
with the outside, these circuits having various control functions related to buses, external cache, and main memory.
 Status signals are extremely diverse, they varying from microprocessor to microprocessor, but their functions can be
classified according to the information provided. Thus, status signals may indicate:

 Type of the current (ongoing) machine cycle.

 Information about internal registers involved in address calculation.
 Synchronization information with other bus master modules (e.g., lock type).
 The state of the internal buffer (cache, queue), useful information for the controller circuit of
both memory and external cache.
 Etc.
 Control Bus

Utility signals

Several types of utility signals are included in this

category, among which:
 signals that bring the processor into a
predetermined state (RESET),
 clock signals (CLOCK)
 power supply.

Clock signals are generated by an internal or external oscillator based on a quartz crystal, external to the
processor. On some microprocessors, the clock circuits can also "synchronize" external signals, with asynchronous
characteristics, such as: RESET and READY.

 There may be crystals equivalent to parallel and serial resonant circuits (RLC) – manufacturers specify whether
the crystals are resonant in series or parallel.
 The next figure shows two ways to connect quartz crystals to the microprocessor chip (the first image is the
commonly used connecting approach encountered in microprocessors with internal oscillator).