CHAPTER 1

PART 2

Topics to be covered
• Interconnection structures
 bus interconnection
 Multiple-Bus Hierarchies
• Peripheral Component Interconnect (PCI)

1
Interconnection Structures
o A computer consists of a set of components or
modules of three basic types (processor,
memory, I/O) that communicate with each
other.
o The collection of paths connecting the various
modules is called the interconnection
structure.
o The design of this structure will depend on the
exchanges that must be made among modules.
o Figure below suggests the types of exchanges.
2
 Memory: Typically, a
memory module will consist
of N words of equal length.
 Each word is assigned a
unique numerical address
(0, 1, . . . ,N – 1).
 A word of data can be read
from or written into the
memory.
 The nature of the operation
is indicated by read and
write control signals.
 The location for the
operation is specified by an
address. 3
 I/O module: From an
internal (to the computer
system) point of view, I/O
is functionally similar to
memory.
 There are two operations,
read and write.
 Further, an I/O module
may control more than one
external device.
 We can refer to each of the
interfaces to an external
device as a port and give
each a unique address (e.g.,
0, 1, . . . ,M– 1) 4
 Processor:
 The processor reads
instructions and data,
writes out data after
processing.
 It uses control signals
to control the overall
operation of the
system.
 It also receives
interrupt signals. 5
 Types of transfers
 The interconnection structure must support the following
types of transfers:
1. Memory to processor: The processor reads an
instruction or a unit of data from memory.
2. Processor to memory: The processor writes a unit of
data to memory.
3. I/O to processor: The processor reads data from an I/O
device via an I/O module.
4. Processor to I/O: The processor sends data to the I/O
device.
5. I/O to or from memory: For these two cases, an I/O
module is allowed to exchange data directly with memory,
without going through the processor, using direct memory
access (DMA). 6
Over the years, a number of
interconnection structures have been
tried. By far the most common is the
bus and multiple-bus structures.

7
 I. BUS INTERCONNECTION
o A bus is a communication pathway connecting two or more
devices.
o A key characteristic of a bus is that it is a shared transmission
medium.
o Each line is capable of transmitting signals representing binary 1
and binary 0.
o Over time, a sequence of binary digits can be transmitted across a
single line.
o Taken together, several lines of a bus can be used to transmit
binary digits simultaneously (in parallel).
o For example, an 8-bit unit of data can be transmitted over eight
bus lines.
o A bus that connects major computer components (processor,
memory, I/O) is called a system bus. 8
 Bus Structure
o A system bus consists, typically, of from about 50 to
hundreds of separate lines.
o Each line is assigned a particular meaning or function.
o Although there are many different bus designs, on any bus
the lines can be classified into three functional groups
 data,
 address, and
 control lines

9
Cont…
o In addition, there may be power
distribution lines that supply power to the
attached modules.

10
Cont…
1. Data Bus
o In computer architecture, the data bus is a wired
connection dedicated for transmitting the data.
o The data bus is a part of the system bus in addition to
address bus and control bus.
o A data bus has many future, but one of the most important
feature is the bus width.
o The width of a data bus refers to the number of bits
(electrical wires) that the bus is can carry.
o The common data bus widths include 8 bit, 16 bit, 32 bit
and 64 bit.
 The wider the bus width, faster would be the data flow on
the data bus and thus beater system performance. 11
 Cont…
2. Address Bus
o The address bus is the set of wire traces that is used to
identify which address in memory the CPU is accessing.
o A collection of wires connecting the CPU with main
memory that is used to identify particular locations
(addresses) in main memory.
o The width of the address bus (that is, the number of wires)
determines how many unique memory locations can be
addressed.
o It is a unidirectional bus, which is to say that data travels
only one way; from the CPU to memory.
o An address bus is part of the system bus architecture
12
 Cont…
3. Control bus
o The Cup(Microprocessor) contains a control unit which
controls the functioning of all other components connected
to the computer system.
o The control bus is used to transfer the control signal from
one component to another component.
o A control bus is a computer bus that is used by the CPU
to communicate with the devices that are connected to he
computer system.
o These components are connected with the help of cables
and printed circuits board such as motherboard.
o The control bus is a part of system bus in addition to data
bus and address bus. 13
Cont…

14
 II. Multiple-Bus Hierarchies
 If a great number of devices are connected to the
bus, performance will suffer. There are two main
causes:
1. propagation delay
 In general, the more devices attached to the bus, the
greater the bus length and hence the greater the
propagation delay.
 This delay determines the time it takes for devices to
coordinate the use of the bus.
 When control of the bus passes from one device to
another frequently, these propagation delays can
noticeably affect performance. 15
 Cont…
2. Capacity of the bus
The bus may become a bottleneck as the
aggregate data transfer demand approaches
the capacity of the bus.
This problem can be countered to some extent
by increasing the data rate that the bus can
carry and by using wider buses (e.g.,
increasing the data bus from 32 to 64 bits).
16
o Multiple-Bus Hierarchies can have two
architectures
a. Traditional bus architecture
b. High Speed or high performance architecture

17
a. Traditional bus architecture
 Use of a cache structure insulates CPU from frequent accesses
to main memory.
 Expansion bus interface buffers data transfers between system
bus and I/O controllers on expansion.

 This traditional bus architecture is reasonably efficient but begins to break

down as higher and higher performance is seen in the I/O devices. 18
 b. High Speed/performance architecture
 A high-speed bus arrangement specifically
designed to support high-capacity I/O devices
 Bring high-demand devices into closer integration
with processor.

19
oThe advantage of this arrangement is
that the high-speed bus brings high
demand devices into closer
integration with the processor and at
the same time is independent of the
processor.

20
Peripheral Component Interconnect (PCI)
o PCI is a popular high-bandwidth, processor-
independent bus that can function as a peripheral bus.
o Compared with other common bus specifications,
PCI delivers better system performance for high-
speed I/O subsystems .
o The current standard allows the use of up to 64 data
lines at 66 MHz, for a raw transfer rate of 528
MByte/s, or 4.224 Gbps.
o PCI requires very few chips to implement and
supports other buses attached to the PCI bus.
 PCI products built by different vendors are
compatible. 21
Reading Assignment

 PCI Buss Structure

 computer organization and architecture by
william stallings (Text book)
 page 95

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