BUS SYSTEMS

What is a Bus?

 Bus is:

 shared communication link

 single set of wires used to connect multiple subsystems

Processor Input

Control
Memory

Datapath
Output

Bus Representation

 Method of transmitting data from one part of the computer to

another part of the computer.
 Buses are the basic transportation lines for moving data, instructions,
addresses, and other information inside a computer.
 Generally the computer bus will connect all devices to the computer
CPU and main memory.
 The word bus comes from the Latin adjective omnibus, meaning all or
everyone.
 A bus is a set (group) of parallel lines on which information (data,
addresses, instructions, and other information) travels on inside a
computer.
 Information travels on buses as a series of electrical pulses, each pulse
representing a one bit or a zero bit (there are trinary, or three-state,
buses, but they are rare).
 Buses are the links between components of a computer system, and
they are often the performance bottleneck in the system.

Advantages of Buses
 Processor I/O I/O Memory
Device Device

o New devices can be added easily.

o Peripherals can be moved between computer systems that use the same
bus standard.
o A single set of wires is shared in multiple ways.

Disadvantages of Buses

o Bus creates a communication bottleneck because the bandwidth of the

bus can limit the maximum I/O throughput.
o The maximum bus speed is largely limited by:

1. The length of the bus

2. The number of devices on the bus
3. The need to support a range of devices with widely varying
latencies

o Widely varying data transfer rates.

The General Organization of a Bus

Control Lines

Data Lines

General Organization of a Bus

Control Lines

o Signal requests and acknowledgements.

o Indicate what type of information is on the data lines.
 Data Lines

o Carry information between the source and the destination:

1. Data and addresses

2. Complex commands

Master Versus Slave

Master Issues Command

Bus Bus
Master Slave

Data can go Either Way

Master Versus Slave Representation

 A bus transaction includes two parts:

1. Issuing the command (and address) - request

2. Transferring the data - action

 Master is the one who starts the bus transaction by:

 Issuing the command (and address)

 Slave is the one who responds to the address by:

 Sending data to the master if the master ask for data

 Receiving data from the master if the master wants to send data

PC Bus Hierarchy

Processor Bus

o This is the highest-level bus that chipset uses to send information to and
from processor.
o A processor bus is a bus inside the processor.
o Processor bus can be further categorized into:

1. Single processor bus

2. Dual processor bus
 1. Single Processor Bus

o All information is carried around inside the processor on one

processor bus.

2. Dual Processor Bus

o Inside a dual processor bus system, there is a source bus

dedicated for moving source data.
o A destination bus is dedicated for moving results.
o An alternative approach is to have a lot of small buses that
connect various units inside the processor.
o While this design is more complex, it also has the potential of
being faster, especially if there are multiple units within the
processor that can perform work simultaneously (a form of
parallel processing).

Memory Bus

o This is a second-level system bus that connects the memory subsystem to

the chipset and the processor.
o In some systems the processor and memory buses are basically the same
thing.

 Processor-Memory Bus (design specific)

 Short and high speed

 Only need to match the memory system

 Maximize memory-to-processor bandwidth

 Connects directly to the processor

 Optimized for cache block transfers

Local I/O Bus

o A high speed input/output bus used for connecting performance-critical

peripherals to the memory, chipset, and processor, e.g., video cards, disk
storage devices, high speed networks interfaces generally use a bus of this
sort.
o The two most common local I/O buses are the VESA Local Bus (VLB)
and the Peripheral Component Interconnect (PCI) Bus.

Standard I/O Bus

 o Connects to the prior three buses.
o It is the “good old” standard I/O bus, used for slower peripherals (mice,
modems, regular sound cards, low-speed networking cards) and also for
compatibility with older devices.
o On almost all modern PCs this is the Industry Standard Architecture
(ISA) Bus.

 I/O Bus (industry standard)

 Usually lengthy and slower

 Need to match a wide range of I/O devices
 Connects to the processor-memory bus or backplane bus

Backplane Bus

o Backplane Bus (standard or proprietary)

 Backplane is an interconnection structure within the chassis

 Allow processors, memory, and I/O devices to coexist

Advantage

o One bus for all components.

A Computer System with One Bus (Backplane Bus)

Backplane

Processor Memory

I/O Devices

Backplane Bus Representation

 A small number of backplane buses tap into the processor-memory bus.

 Processor-memory bus is only used for processor-memory traffic

  I/O buses are connected to the backplane bus

 The Backplane bus’s example is IBM PC - AT

Uses

o A single bus (the backplane bus) is used for:

 Processor to memory communication

 Communication between I/O devices and memory

Advantages

o Simple and low cost.

o Loading on the processor bus is greatly reduced.

Disadvantage

o Slow and the bus can become a major bottleneck.

A Two-Bus System

Processor Memory Bus

Processor Memory

Bus Bus Bus

Adaptor Adaptor Adaptor

I/O I/O I/O

Bus Bus Bus

Two-Bus System Representation

  I/O buses tap into the processor-memory bus via bus adaptors:

 Processor-memory bus is mainly for processor-memory traffic

 I/O buses provide expansion slots for I/O devices

 The two bus system’s example is Apple Macintosh-II

 NuBus is for processor, memory, and a few selected I/O devices

 SCCI Bus is for the rest of the I/O devices

A Three-Bus System (+ Backside Cache)

Processor Memory Bus

Processor Memory

Backside Bus
Cache Bus Adaptor

Bus
L2 Adaptor
Cache
I/O Bus

I/O Bus
Bus
Adaptor

Three-Bus System (+ Backside Cache) Representation

What Defines a Bus?

 Transaction protocol
  Timing and signaling
 Bunch of wires
 Electrical specification
 Physical/mechanical characteristics – the connectors

Synchronous and Asynchronous Buses

Synchronous Bus

o Includes a clock in the control lines.

o A fixed protocol for communication that is relative to the clock.

Advantage

o They run at very fast speed.

Disadvantages

o Every device on the bus must run at the same clock rate.
o To avoid clock skew, they cannot be long if they are fast.

Asynchronous Bus

o It is not clocked.
o It requires a handshaking protocol.

Advantages

o It can accommodate a wide range of devices.

o It can be lengthened without worrying about clock skew.

Buses so Far

Master Slave ooo

Control Lines
Address Lines
Data Lines
 Bus Master

o Has ability to control the bus, initiates transaction.

Bus Slave

o Module activated by the transaction.

Bus Communication Protocol

o Specification of sequence of events and timing requirements in

transferring information.

Asynchronous Bus Transfers

o Control lines (request, acknowledgement) serve to orchestrate sequencing.

Synchronous Bus Transfers

o Sequence relative to common clock.

Bus Transaction

Arbitration

o Who gets the bus?

Request

o What do we want to do?

Action

o What happens in response?

Arbitration (Obtaining Access to the Bus)

Control: Master Initiates Requests

Bus Bus
Master Slave

Data can go Either Way

Master Versus Slave Representation

  One of the most important issues in bus design:

 How is the bus reserved by a device that wishes to use it?

 Chaos is avoided by a master-slave arrangement:

 Only the bus master can control access to the bus:

 It initiates and controls all bus requests

 A slave responds to read and write requests

The Simplest System

o Processor is the only bus master.

o All bus requests must be controlled by the processor.

Major Drawback

o The processor is involved in every transaction.

Multiple Potential Bus Masters (The Need for Arbitration)

Bus Arbitration Scheme

o A bus master wanting to use the bus asserts the bus request.
o A bus master cannot use the bus until its request is granted.
o A bus master must signal to the arbiter after using the bus.

 Bus arbitration schemes usually try to balance two factors:

1. Bus Priority

o The highest priority device should be serviced

first.

2. Fairness

o Even the lowest priority device should never be

completely locked out from the bus.

 Bus arbitration schemes can be divided into four broad classes:

 1. Daisy chain arbitration
2. Centralized, parallel arbitration
3. Distributed arbitration by self-selection
4. Distributed arbitration by collision detection

1. The Daisy Chain Bus Arbitrations Scheme

Device 1 Device N
Highest Device 2 ooo Highest
Priority Priority

Grant Grant Grant

Release
Bus
Arbiter
Request

Daisy Chain Bus Arbitrations Representation

Advantage

o Simple.

Disadvantages

o A low-priority device may be in waiting state

indefinitely to get access of the bus.
o The use of the daisy chain grant signal also limits
the bus speed.

2. Centralized Parallel Arbitration

Device 1 Device 2 ooo Device N

Grant

Request Grant
Request Grant
Bus
Arbiter Request
 Release
o Used in essentially all processor-memory buses
and in high-speed I/O buses.
Centralized Parallel Arbitration Representation
3. Distributed Arbitration by Self-Selection

o Each device wanting the bus places a code

indicating its identity on the bus.

4. Distributed Arbitration by Collision Detection

o Each device just “goes for it”.

o Problems found after the fact.

Simplest Bus Paradigm

ooo

Simplest Bus Paradigm

 All agents operate synchronously.

 All can source/sink data at same rate
 Simple protocol

 Just manage the source and target

Simple Synchronous Protocol

o Even memory buses are more complex

 Memory (slave) may take time to respond

o It may need to control data rate

Typical Synchronous Protocol

 o Slave indicated when it is prepared for data transfer
o Actual transfer goes at bus rate

Increasing the Bus Bandwidth

Separate Versus Multiplexed Address and Data Lines

o Address and data can be transmitted in one bus cycle if separate address
and data lines are available.

Disadvantages

o More bus lines.

o Increased complexity.

Data Bus Width

o By increasing the width of the data bus, transfers of multiple words

require fewer bus cycles, e.g., SPARC Station 20’s memory bus is 128 bit
wide.

Single Cycle Transfer

Address Data Address Data Address Data

Single Cycle Transfers

o Normally every single bus cycle requires an address to be transferred

followed by the datum.

Disadvantage

o Inefficient technique.

Block Transfers

Address Data Data Data

 Burst Transfer

o Allow the bus to transfer multiple words in back-to-back bus cycle.

o Only one address needs to be sent at the beginning, followed by the
complete block of data, as it is stored at consecutive memory locations.

Advantage

o Decreased response time for request.

Disadvantage

o The bus is not released until the last word is transferred.

 Once a burst has started, requesting masters have to wait until the
burst has finished, which could take a relatively long time.

 Solution to Overcome the Disadvantage

o Pre-emption can be used to overcome this disadvantage.

 This means that the current bus master is signaled

when a potential master with a higher priority is
requesting the bus.
 When the current master receives this signal, it
stops its burst and releases the bus, to continue later
on.

Asynchronous Handshake

Write Transaction

o Master has obtained control and asserts address, direction, and data.

 Waits for a specified amount of time, for slaves to decode target.

o Slave asserts acknowledgement, indicating that data is received.

Read Transaction

o Master has obtained control and asserts address, direction, and data.

 Waits for a specified amount of time, for slaves to decode target.

 o Slave asserts acknowledgement, indicating ready to transmit data.

PCI Bus

 PCI is the abbreviation of Peripheral Component Interconnection.

 Peripheral Component Interconnect – developed by Intel Corporation.
 PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus.
 It can run at clock speeds of 33 or 66 MHz.
 At 32-bits and 33 MHz, it yields a throughput rate of 133 MBps.
 The 64-bit PCI Bus with 66 MHz yields throughput rate of 508.6 MBps.
 Push bus efficiency towards 100% under common simple usage

USB

 USB is the abbreviation of Universal Serial Bus.

 A new external bus standard that supports data transfer rates of 12 Mbps
(12 million bits per second).
 A single USB port can be used to connect up to 127 peripheral devices, such
as mice, modems, and keyboards.
 Supports Plug-and-Play installation.

How Universal Serial Bus (USB) Operates?

o USB uses a small, flat jack and thin cable to connect peripherals to the
host PC.
o The system automatically detects when a USB device is added or
subtracted from this bus.
o Up to 127 devices may be chain-connected to a single USB connection to
the system.
o The host PC begins the USB chain, but peripherals such as keyboards
and monitors that might come equipped with multiple USB ports could
become a USB hub for connecting more devices.

USB Speeds

o USB offers a pair of speeds

 1.5 Mbits per second for low-speed devices such as keyboards,

mice and joysticks.
 12 Mbits per second at the high-end for scanners, printers,
monitors and telephones.

ISA
  IBM introduced ISA or Industry Standard Architecture Bus.
 It was originally released as an 8-bit bus, however was expanded to 16-bit
bus in 1984.
 In 1993, Intel and Microsoft introduced a PnP ISA Bus, which allows the
computer to automatically detect and setup computer ISA peripherals such
as a modem or sound card.

MCA

 IBM introduced MCA or the Micro Channel Bus in 1987 as a competition for
ISA Bus.
 The MCA Bus offered several additional features over the ISA such as:

 A 32-bit bus
 Automatically configure cards (similar to what Plug and Play is
today)
 Bus mastering for greater efficiency

 Not backward compatible with ISA.

 MCA Bus was released as a proprietary bus which only allowed IBM to
create the cards for its own bus.
 Because of these two major factors the MCA Bus never became widely used.

EISA

 Extended Industry Standard Architecture (EISA) announced in September

of 1988 – is a bus designed by 9 competitors to compete with IBM’s MCA
Bus.
 These competitors were AST Research, Compaq, Epson, Hewlett Packard,
NEC, Olivetti, Tandy, WYSE and Zenith Data Systems.
 The EISA Bus provided 32-bit slots at an 8.88 MHz cycle rate for use with
386DX or higher processors.

Addressing

 Once a bus master controls a bus, it must establish contact with one or more
slaves in order to set up the data transfer.
 This is called addressing, which potentially consists of two parts: board
addressing and the addressing of the data elements on that board.
 Often, the same mechanism is used for both.
 Each board is allocated a block of addresses such that the high-order address
bits specify the board and the low-order bits of the same address specify the
data element on the board.
 The subject of addressing is discussed in terms of how a slave address can be
specified and the number of slaves involved in a bus transaction.

Slave Address Specification

o During a bus operation, the address of the slave to be involved in the

operation is specified via the address lines of the bus.
o The address of the slave is usually the address of the slave’s board.
o Each device, therefore, has a unique address.
o When this matches the address specified via the address lines, the device
is said to be selected.
o Two methods can be distinguished for allocating board addresses: logical
(location-independent) addressing and geographical (location-dependent)
addressing.
o Logical addressing means that each device is given a unique address or
group of addresses, for example; this address can be given in a completely
arbitrary way, it does not depend on, for example, the type of the device
or its position in the backplane.
o This requires extra hardware and may also require human interaction to
customize the device address.
o Geographical addressing means that a device may be addressed by its
physical location, which is where a device is inserted in the backplane.
o This location is called the slot number and is hard-wired into the
backplane, rather than via customizable hardware.
o Geographical addressing allows for location independence of the devices
and for operating system-initiated reconfiguration of the system.
o The operating system can use geographical addressing as part of its
initialization sequence to set up logical addresses which are stored in an
address register on the board, such that customizing the address is done
completely under software control.
o The logical addresses are subsequently used by all bus transactions.
o Essentially, geographical addressing allows the allocation of logical device
addresses under software control.

Number of Slaves Involved in a Bus Transaction

o Most bus transactions require only a single slave to be involved in the bus
transaction.
o However, for certain bus transactions, such as reset, it may be desirable
to involve all slaves or a group of slaves.
o Read and write operations that may involve more than one slave are
called broadcall and broadcast operations, respectively.
o The concept of broadcast/broadcall addressing is orthogonal to
logical/geographical addressing; it deals with the communication of a
single master with multiple slaves.
o Broadcall operations cause all selected slaves to place their data on the
bus, which will result in the collective AND or OR of the data of the
selected slaves.
o This restricts the use of broadcall addressing to special cases; for
example, to identify the source of an interrupt where each potential
interrupter is assigned a single-bit position to identify itself.
o A broadcall on a 32-bit bus can then be used to identify up to 32 interrupt
sources.
o Broadcast operations are important for performance reasons; for
example, in the case of data consistency, when several caches in a
multiprocessor system with distributed caches have to be updated
simultaneously.
o The reset operation, where each device is expected to assume its initial
state, is also a form of broadcast operation.
o Broadcast/broadcall operations can be indicated via a special address (for
example, address 0) or via a special control line, in which case the address
lines can be used to select a subset of all slaves.