Module 1

BUS Interconnection
BUS Interconnection
All the units must be connected
Different types of connection for different
types of unit
◦ Memory
◦ Input / Output
◦ CPU

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Computer Modules

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Memory Connection
Receives and sends data
Receives addresses (of locations)
Receives control signals
◦ Read
◦ Write
◦ Timing

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Input/Output Connection
Similarto memory from computer’s
viewpoint
Output
◦ Receive data from computer
◦ Send data to peripheral
Input
◦ Receive data from peripheral
◦ Send data to computer

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Input/Output Connection(2)
Receive control signals from computer
Send control signals to peripherals

◦ e.g. spin disk

Receive addresses from computer
◦ e.g. port number to identify peripheral
Send interrupt signals (control)

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CPU Connection
Reads instruction and data
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts

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Buses
There are a number of possible interconnection
systems
Single and multiple BUS structures are most
common
e.g. Control/Address/Data bus (PC)

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What is a Bus?
A communication pathway connecting two or
more devices
Shared transmission medium.
Usually broadcast
Often grouped

◦ A number of channels in one bus

◦ e.g. 32 bit data bus is 32 separate single bit
channels
Power lines may not be shown

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Data Bus
Carries data
◦ Remember that there is no difference between
“data” and “instruction” at this level
Width is a key determinant of
performance
◦ 8, 16, 32, 64 bit

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Address bus
Identify the source or destination of data
◦ e.g. CPU needs to read an instruction (data)
from a given location in memory
Bus width determines maximum memory
capacity of system
◦ e.g. 8080 has 16 bit address bus giving 64k
address space

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 Control Bus
Control and timing information
◦ Timing signals indicate the validity of data and
address information
 Memory read/write signal
 Interrupt request
 Clock signals

◦ Command signals specify operations to be

performed

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Bus Interconnection Scheme

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Control lines

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 Bus Operation
 If one module wishes to send data to another, it must do two
things:
1) obtain the use of the bus, and
2) transfer data via the bus.
 If one module wishes to request data from another module, it
must
1) obtain the use of the bus, and
2) transfer a request to the other module over the
appropriate control and address lines. It must then wait
for that second module to send the data.

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What do buses look like?
◦ Parallel lines on circuit boards
◦ Ribbon cables
◦ Strip connectors on mother boards
 e.g. PCI  Peripheral Component Interconnect
◦ Sets of wires

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 Single Bus Problems
Lots of devices on one bus leads to:
◦ Propagation delays
 Long data paths mean that co-ordination of bus use can
adversely affect performance
 If aggregate data transfer approaches bus capacity
Most systems use multiple buses to
overcome these problems

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Traditional Bus

Small Computer
System Interface

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High Performance Bus

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Elements of Bus Design

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Bus Types
Dedicated
◦ Separate data & address lines
Multiplexed
◦ Shared lines
◦ Address valid or data valid control line
◦ Advantage - fewer lines ( save space & cost)
◦ Disadvantages
 More complex control circuit
 Reduction in performance

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Physical dedication- use of multiple buses, each
of which connects only a subset of modules.
Ex I/O bus to interconnect all I/O modules
Adv: High Throughput
Disadvantage : size, cost

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Bus Arbitration
More than one module controlling the bus
◦ e.g. CPU and DMA controller
Only one module may control bus at one
time
Arbitration may be centralised or
distributed

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Centralised Arbitration
Single hardware device controlling bus
access
◦ Bus Controller
◦ Arbiter
May be part of CPU or separate

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 Distributed Arbitration
Each module may claim the bus
Control logic on all modules
With both methods of arbitration, the
purpose is to designate one device, either the
processor or an I/O module, as master.
The master may then initiate a data transfer
(e.g., read or write) with some other device,
which acts as slave for this particular
exchange.
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Timing
Timing refers to the way in which events
are coordinated on the bus.
 Buses use either synchronous timing or
asynchronous timing

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Timing of synchronous bus operation

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Timing of synchronous bus operation

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29
 Moore’s Law
 Moore's Law is a computing term which originated around
1970; the simplified version of this law states that
processor speeds, or overall processing power for
computers will double every two years.
Transistor counts