A Presentation On

“Analysis, Design And Implementation of Programmable Electronic

Load for Testing of Various Sources”

Mid Sem Review

Date:13/03/2018

Electrical Engineering Department

M.E Sem - IV
Sarvajanik College of Engineering and Technology, Surat

GUIDED BY: PREPARED BY:

PROF. (DR.) SHABBIR S. BOHRA KANADHIYA MANALI C.(160420707005)
 OUTLINE
• Introduction
• Problem Identification
• Solution
• Introduction of Active Programmable Electronic Load
• Basic Block Diagram of APEL
• Detailed Block Diagram of APEL
• Control Strategy
• Previous Work
• Comments in DP-1
• Work Done
• Future Work
• Conclusion
• References

12/24/2020 S.C.E.T,SURAT 2
 INTRODUCTION

 Some electronic devices such as uninterruptible power systems (UPS), transformers, power supplies or

energy storage systems need to be tested, to check the behaviour of the equipment and to improve its

reliability and stability.

 This burn-in test is an essential step during the manufacture process of equipment.

 The traditional method used to perform these tests consists of resistors, capacitors, inductors, trying to

reproduce the desired load profile defined by the end-user or standards for the given applications.

12/24/2020 S.C.E.T,SURAT 3
 PROBLEM IDENTIFICATION

 In this traditional method, load bank is usually designed with dissipative components, resistors,

inductors and capacitors, which generate a lot of power losses and hence heat. For high power

applications these power losses are unacceptable.

 Every time different load configurations are required, this will increase the test time and high operating

costs.

 Large energy consumption during test.

 Energy in testing is wasted and operation is inconvenient.

12/24/2020 S.C.E.T,SURAT 4
 SOLUTION

 To reduce these problems an alternative is to use ACTIVE PROGRAMMABLE

ELECTRONIC LOADS.

12/24/2020 S.C.E.T,SURAT 5
 INTRODUCTION OF ACTIVE PROGRAMMABLE ELECTRONIC LOAD

 Electronic loads have been developed and commercialized to extend the conditions of the test, as
variable resistances, constant power, constant current, and constant voltage modes of operation,
and even as non-linear loads.
 Desired programmable ac load is expected to cover a variety of load profiles, such as
programmable power factor (R, L, C load) and harmonic load profiles.
 For conventional approaches of achieving harmonic load profiles, passive six pulse and twelve-
pulse diode rectifiers are typically used.
 With the recent advancement of power electronic technology and semiconductor device, load
emulation based on power electronic circuit, for example: a Voltage Source Inverter (VSI) has
been made possible.

12/24/2020 S.C.E.T,SURAT 6
 BASIC BLOCK DIAGRAM

AC AC AEL DC
SOURCE EUT
CONVERTER LINK

CURRENT
CONTROL

Fig. 1 Basic Architecture of APEL

 The basic blocks of an AC APEL are power source and an electronic converter that draws the power from
the EUT according to desired load behaviour.
 Here, the EUT means equipment under test that we can test various sources such as UPS, AC regulator,
generator, transformer etc.
 The control is done by user to achieve desired load profile.
12/24/2020 S.C.E.T,SURAT 7
 OBJECTIVE OF THE PROJECT

 The main objective of the project is to design an AC active programmable electronic load.
 To develop a control structure that emulate harmonic load behaviours.

12/24/2020 S.C.E.T,SURAT 8
 DETAILED BLOCKDIAGRAM[1]

Fig. 2 System Architecture of the APEL

12/24/2020 S.C.E.T,SURAT 9
 CONTROL STRATEGY FOR HARMONIC LOADS EMULATION [1]

VEUT

IEUT

Fig. 3 Diagram of Control strategy

12/24/2020 S.C.E.T,SURAT 10
 HARMONIC CALCULTION

1. Positive sequence harmonics: 2. Negative sequence harmonics: 3. Zero sequence harmonics:

+ve seq. 7,13.19, -ve seq. 5,11,17,23 zero seq. 3,9,15,21

harmonics and so on harmonics and so on harmonics and so on

Fig. 4 Vector representation of effects of sequences on harmonics

12/24/2020 S.C.E.T,SURAT 11
 REFERENCE CURRENT GENERATION

1. Fundamental + Positive sequence harmonics: 2. Fundamental + Negative sequence harmonics:

Fig .5 vector representation of +Ve sequence harmonics Fig .6 vector representation of -Ve sequence harmonics
Id = 1× sin θ + Ip×sin {(n-1) ωt + θ } Id = 1 + In × sin {(n+1) ωt - 90°}
= 1 + Ip × sin {(n-1)ωt + 90°} = 1 + In × sin {(n+1)ωt - 90°}
Iq = Ip × sin {(n-1)ωt} Iq = In × sin {(n+1)ωt}
Where, Ip=0.2 Where, In=0.2
12/24/2020 S.C.E.T,SURAT 12
 SIMULATION CIRCUIT

Fig.7 main simulation diagram

12/24/2020 S.C.E.T,SURAT 13
SIMULATION PARAMETERS:
Vabc(line to line)=110V
RLPR=0.25Ω Fig.8 simulation circuit of control strategy
LLPR=1mH
Cdc=470µF
12/24/2020 S.C.E.T,SURAT 14
 SUBSYSTEM-1 SEQUENCE ANALYSIS

Fig.9 Sequence analysis

12/24/2020 S.C.E.T,SURAT 15
 SUBSYSTEM-2 MAGNITUDE AND ANGLE TO SINEWAVE

Fig.10 Magnitude & angle to sinewave

12/24/2020 S.C.E.T,SURAT 16
 SUBSYSTEM-3 ABC TO DQ0 TRANSFORMATIONS

Fig. 14 abc to dq0

Fig.11 abc to dq0 transformations

12/24/2020 S.C.E.T,SURAT 17
 SUBSYSTEM-4 REFERENCE AND MEASURED CURRENT

Fig.12 reference & measured current circuit

R , L , C , 5th , 7th , 3rd , F+2

12/24/2020 S.C.E.T,SURAT 18
 SUBSYSTEM-5 PI CONTROLLER

Fig.13 PI controller

12/24/2020 S.C.E.T,SURAT 19
 SUBSYSTEM-6 DQ0 TO ABC

Fig.14 dq0 to abc transformations

12/24/2020 S.C.E.T,SURAT 20
 SUBSYSTEM-7 REFERENCE CURRENT FOR LOAD PROFILE RECTIFIER

Fig.15 Reference current for hysteresis current controller

Fig.16 hysteresis current controller

12/24/2020 S.C.E.T,SURAT 21
 SIMULATION RESULTS

Case 1: Resistive load

Case 2: Inductive load

Case 3: capacitive load

Work done till DP-1
Case 4: Resistive load with step change

Case 5: (Fundamental + 5th harmonic) load

Case 6: (Fundamental +7th harmonic) load

Case 7: (Fundamental +3rd harmonic) load

Case 8: (Fundamental + two harmonic) load

Work done
Case 9: Emulation of six pulse diode rectifier

Case 10: Emulation of twelve pulse diode rectifier

12/24/2020 S.C.E.T,SURAT 22
 Workdone till DP-1 CASE 1: RESISTIVE LOAD (SUBSYSTEM 4)
Iabc.ref (A)
2

Iabc.ref (A)
4
Ia(without filter) (A) Ia(A)
Ia.ref (A) 0 Ib (A)
2 Ia(withfilter)(A)
Ic (A)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Ia (A)

0 time (s)
Iabc (without filter) (A)
2

Iabc (A)
-2
0
-4 -2
0.02 0.04 0.06 0.08 0.1 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s) time (s)
Iabc (with filter) (A)
2

Iabc (A)
0

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
Fig.17 reference current and source current for R load

12/24/2020 S.C.E.T,SURAT 23
 CASE 1: RESISTIVE LOAD
Ideal source current Iabc(A) of resistive load 2
FFT window: 4 of 5 cycles of selected signal
2 0
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Iabc(A)

Ia(A) Time (s)

0 Ib(A) Fundamental (50Hz) = 1.91 , THD= 8.51%

Mag (% of Fundamental)
Ic(A) 0.4

0.2
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0
time(s) 0 100 200 300 400 500
Frequency (Hz)
600 700 800 900 1000

Source current Iabc(A) of resistive load with APEL

2 FFT window: 4 of 5 cycles of selected signal
2
Iabc (A)

0 -2
0.02 0.03 0.04 0.05 0.06
Time (s)
0.07 0.08 0.09

Fundamental (50Hz) = 1.91 , THD= 3.34%

Mag (% of Fundamental)
-2 0.4
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.2
time (s)
0
0 100 200 300 400 500 600 700 800 900 1000
Fig.18 Ideal source current Iabc(A) for Inductive load and Frequency (Hz)

source current Iabc(A) for Inductive load with APEL

Fig.19 FFT analysis
12/24/2020 S.C.E.T,SURAT 24
 CASE 2: INDUCTIVE LOAD (SUBSYTEM 4)

Iabc.ref (A)
4 2

Iabc.ref (A)
Ia (without filter) (A)
0
Ia.ref (A)
2 Ia (with filter) (A) -2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
Iabc (without filter) (A)
Ia (A)

0 2

Iabc (A)
0
-2
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
-4 2 Iabc (with filter) (A)
0.02 0.04 0.06 0.08 0.1

Iabc (A)
time (s)
0

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)

Fig.20 reference current and source current for inductive load

12/24/2020 S.C.E.T,SURAT 25
 FFT ANALYSIS OF INDUCTIVE LOAD

Ideal source current Iabc(A) of inductive load  THD values:

2
Ia(A)
(Without filter) 8.93%
Iabc(A )

Ib(A)
0 Ic(A) APEL
(With filter) 3.70%
-2 APEL
0.02 0.03 0.04 0.050.06 0.07 0.08 0.09 0.1
time (s)
Source current Iabc(A) of inductive load with APEL
2
Iabc (A )

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)

Fig.21 Ideal source current Iabc(A) for capacitive load and

source current Iabc(A) for inductive load with APEL

12/24/2020 S.C.E.T,SURAT 26
 CASE 3: CAPACITIVE LOAD (SUBSYSTEM 4)
Iabc.ref (A)
4 2

Iabc.ref (A)
Ia (without filter) (A) Ic (A)
Ia.ref (A) 0 Ia (A)
2 Ia(with filter) (A) Ib (A)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
Ia (A)

0 Iabc(without filter) (A)

2

Iabc (A)
0
-2
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-4 time (s)
0.02 0.04 0.06 0.08 0.1 Iabc(with filter) (A)
2
time (s)

Iabc (A)
0

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)

Fig.22 reference current and source current for capaitive load

12/24/2020 S.C.E.T,SURAT 27
 FFT ANALYSIS OF CAPACITIVE LOAD

 THD values:
Ideal source current Iabc(A) of capacitive load
2
(Without filter) 8.88%
Iabc(A)

Ia(A)
APEL
0 Ib(A)
Ic(A) (With filter) 3.67%
APEL
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
source current Iabc(A) of capacitive load with APEL
2
Iabc (A)

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)

Fig.23 Ideal source current Iabc(A) for capacitive load and

source current Iabc(A) for capacitive load with APEL

12/24/2020 S.C.E.T,SURAT 28
 CASE 4: RESISTIVE LOAD WITH STEP CHANGE
Iabc.ref (A)
15 5

Iabc (A)
Ia.ref (A) Ia (A)
10 Ia (with filter)(A) 0 Ib (A)
5 Ia(without filter)(A) Ic (A)
-5
Ia (A)

0 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

time (s)
-5 Iabc(without fiter)(A)
5

Iabc (A)
-10
0
-15
0.02 0.04 0.06 0.08 0.1
time (s) -5
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
Iabc(with filter) (A)
5

Iabc (A) 0

-5
0.02 0.03 0.04 0.050.06 0.07 0.08 0.09 0.1
time(s)
Fig.24 reference current and source current for dynamic condition
12/24/2020 S.C.E.T,SURAT 29
 CASE 4: RESISTIVE LOAD WITH STEP CHANGE

Ideal source current Iabc(A) of dynamic resistive loading condition  THD values:
5
(Without filter) 20.98%
Iabc(A)

Ia (A) APEL
0
Ib (A) (With filter) 20.25%
Ic (A) APEL
-5
0.02 0.03 0.04 0.05
0.06 0.07 0.08 0.09 0.1 Ideal 19.85%
time (s)
Source current Iabc(A) of dynamic resistive loading condition with APEL
5
Iabc (A)

-5
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
Fig.25 Ideal source current Iabc(A) for dynamic resistive
loading condition and source current Iabc(A) for dynamic
resistive loading condition with APEL
12/24/2020 S.C.E.T,SURAT 30
 CASE 5 : FUNDAMENTAL+ 5th HARMONIC (SUBSYSTEM 4)
4 Iabc.ref(A)
2

Iabc.ref (A)
Ia.ref (A) Ia(A)
Ia (with filter) (A) 0 Ib(A)
source current (Ia) (A)

2 Ia (without filter) (A) Ic(A)

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (sec)
0 Iabc(without filter)(A)
2

Iabc (A)
-2 0

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-4 time (s)
0.02 0.04 0.06 0.08 0.1 Iabc(with filter)(A)
time (s) 2

Iabc (A)
 THD values:
0
(Without filter) 27.34%
APEL -2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
(With filter) 21.65%
APEL
Ideal 20.20%

12/24/2020 Fig.26 reference current and source current for n=1 and n=5 31
 CASE 5 : FUNDAMENTAL+ 5th HARMONIC (SUBSYSTEM 4)
Ia (A) (without filter)
1
Ideal source current Iabc(A) of n=1 and n=5 0
-1
2 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Time (s)
Iabc(A )

Mag (% of Fundamental)
Fundamental (50Hz) = 1.111 , THD= 27.34%

0 Ia(A) 20

Ib(A) 10

Ic(A) 0
0 100 200 300 400 500 600 700 800 900 1000
-2 Frequency (Hz)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

time (s) 1
Ia (A)(with filter)

Source current Iabc(A) of n=1 and n=5 with APEL 0

-1
2 0.02 0.03 0.04 0.05 0.06
Time (s)
0.07 0.08 0.09

M ag (% of Funda mental)
Iabc (A )

Fundamental (50Hz) = 1.111 , THD= 21.65%

20
15
0 10
5
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1
Ia(A)

time (s) 0
-1
0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06
Time (s)

Fundamental (50Hz) = 1 , THD= 20.00%

Fig.27 Ideal source current Iabc(A) of n=1 and n=5 and

M ag (% of Fundam ental)
20

source current Iabc(A) of n=1 and n=5with APEL 10

0
0 5 10 15 20
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.28 FFT Analysis 32

 CASE 6 : (FUNDAMENTAL + 7th HARMONIC) LOAD (SUBSYTEM 4)

4 Iabc.ref (A)
2

Iabc.ref (A)
Ia.ref (A) Ia (A)
Ia (without filter) (A) 0 Ib (A)
source current Ia (A)

2 Ia (with filter) (A) Ic (A)

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
0 Iabc (without filter) (A)
2

Iabc (A)
0
-2
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
-4 Iabc(with filter) (A)
0.02 0.04 0.06 0.08 0.1 2
time (s)

Iabc (A)
 THD values: 0
(Without filter) 26.20% -2
APEL 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
(With filter) 20.21%
APEL
Ideal 20.20%

Fig.29 reference current and source current for n=1 and n=7
12/24/2020 S.C.E.T,SURAT 33
 CASE 6 : (FUNDAMENTAL + 7th HARMONIC) LOAD (SUBSYTEM 4)
Ideal source current Iabc(A) of n=1 and n=7 Ia (without filter) (A)
2 1
0
-1
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

M a g (% o f F u n d a m e n ta l)
Time (s)
Iabc(A)

0 Ia (A) 20
Fundamental (50Hz) = 1.113 , THD= 26.20%

Ib (A) 10

Ic (A)
0
0 100 200 300 400 500 600 700 800 900 1000
-2 Frequency (Hz)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

time (s) 1
Ia (with fi lter) (A)

0
Source current Iabc(A) of n=1 and n=7 with APEL -1
2 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

M a g ( % o f F u n d a m e n t a l)
Time (s)

Fundamental (50Hz) = 1.113 , THD= 20.21%

20
Iabc (A)

10
0
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

Ia(A)
-2 1
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0
-1
time (s) 0.02 0.025 0.03 0.035 0.04
Time (s)
0.045 0.05 0.055

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1 , THD= 20.00%

Fig.30 Ideal source current Iabc(A) of n=1 and n=7 and 20

source current Iabc(A) of n=1 and n=7 with APEL 10

0
0 5 10 15 20
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.31 FFT Analysis 34

 COMMENTS IN DP-1

 Different sources to be simulated for harmonic analysis purpose.

 Hardware Implementation.
 It is proposed to compare the hardware results with available standard results.

12/24/2020 S.C.E.T,SURAT 35
 Work done CASE 7 : (FUNDAMENTAL + 3rd HARMONIC) LOAD (SUBSYSTEM 4)
2 Iabc.ref (A)
2

Iabc.ref (A)
Ia.ref (A)
Ia (A)
Ia(without filter)(A)
0 Ib (A)
Source current Ia (A)

1 Ia(with filter)(A)
Ic (A)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
0 time (s)
2 Iabc(without filter) (A)

Iabc (A)
-1
0

-2 -2
0.02 0.04 0.06 0.08 0.1 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s) time (s)
Iabc(with filter) (A)
 THD values: 2

Iabc (A)
(Without filter) 25.04% 0
APEL -2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
(With filter) 17.86% time (s)
APEL
Ideal 20.0%
Fig.32 reference current and source current for n=1 and n=3
12/24/2020 S.C.E.T,SURAT 36
 CASE 7 : (FUNDAMENTAL + 3rd HARMONIC) LOAD (SUBSYSTEM 4)
Ia (with out filter) (A)

Ideal source current of n=1 and n=3 1

0
2 -1
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17

M a g (% o f F unda m e nta l)
Time (s)
Iabc(A)

Fundamental (50Hz) = 1.24 , THD= 25.04%

15

0 10

0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Ia (wi th fil ter) (A)
time(s) 1
0

Source current Iabc(A) of n=1 and n=3

-1
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17

2 Time (s)

M a g (% o f Funda m e nta l)
Fundamental (50Hz) = 1.241 , THD= 17.86%
15
Iabc (A)

10

5
0 0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

-2 1 Ia(A)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0

time (s) -1
0.02 0.025 0.03 0.035 0.04
Time (s)
0.045 0.05 0.055

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1 , THD= 20.00%

Fig.33 Ideal source current Iabc(A) of n=1 and n=3 and 20

source current Iabc(A) of n=1 and n=3 with APEL 10

0
0 5 10 15 20
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.34 FFT Analysis 37

 CASE 8 : (FUNDAMENTAL + 5th HARMONIC + 7th HARMONIC) LOAD (SUBSYSTEM 4)
4 Iabc.ref (A)
Ia.ref (A) 2

Iabc.ref (A)
Ia (A)
Ia (with filter) (A)
2 0 Ib (A)
Ia (without filter) (A)
Ic (A)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Ia (A)

0 time (s)
Iabc (without filter) (A)
2
-2

Iabc (A)
0
-4 -2
0.02 0.04 0.06 0.08 0.1 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (s)
time (s)
 THD values: Iabc (with filter) (A)
2

Iabc (A)
(Without filter) 32.91% 0
APEL
-2
(With filter) 28.33% 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
APEL time (s)

Ideal 28.28%

Fig.35 reference current and source current for n=1, n=5, n=7
12/24/2020 S.C.E.T,SURAT 38
 CASE 8 : (FUNDAMENTAL + 5th HARMONIC + 7th HARMONIC) LOAD (SUBSYSTEM 4)
Ia (wi thout fi l ter) (A)

Ideal Source current Iabc(A) of n=1,n=5 and n=7 1

0
2 -1
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

M a g (% o f F unda m e nt a l)
Time (s)
Iabc(A)

Fundamental (50Hz) = 1.113 , THD= 32.91%

0 Ia(A) 20

Ib(A) 10

Ic(A) 0
0 100 200 300 400 500 600 700 800 900 1000
-2 Frequency (Hz)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Ia (with fi lter) (A)
time (s) 1
0

Source current Iabc(A) of n=1,n=5and n=7 with APEL -1

M a g (% o f F unda m e nta l)
2 0.02 0.03 0.04 0.05 0.06
Time (s)
0.07 0.08 0.09

Fundamental (50Hz) = 1.114 , THD= 28.33%

Iabc (A)

20
15

0 10
5
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

-2 Ia(A)
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1
0
time (s) -1
0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06
Time (s)

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1 , THD= 28.28%
Fig.36 Ideal source current Iabc(A) of n=1,n=5 and n=7 20

and source current Iabc(A) of n=1,n=5 and n=7with APEL 10

0
0 5 10 15 20
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.37 FFT Analysis 39

 CASE 9 : EMULATION OF SIX PULSE RECTIFIER
2 Iabc.ref (A)
Ia(without filter)(A) 2
Ia(A)

Iabc(A)
Ia.ref (A)
Ia(with filter)(A)
0 Ib(A)
1
Ic(A)
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Ia(A)

0 time (s)
Iabc(without filter)(A)
2
-1

Iabc(A)
0
-2
0.02 0.04 0.06 0.08 0.1 -2
time(s) 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(s)
 THD values: 2
Iabc(with filter)(A)

Iabc(A)
(Without filter)APEL 28.47% 0

-2
(With filter)APEL 26.31% 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(s)
conventional 30.62%

Fig.38 reference current and source current for six pulse diode rectifier by using APEL
12/24/2020 S.C.E.T,SURAT 40
 CASE 9 : EMULATION OF SIX PULSE RECTIFIER
Ia(without filter)(A) with APEL
Iabc(A) current waveforms of six pulse diode rectifier 1
0
2 -1
0.04 0.042 0.044 0.046 0.048 0.05 0.052 0.054 0.056 0.058
T ime (s)

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1.127 , THD= 28.47%
Iabc(A)

20

0 15

10

0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(s) 1
Ia(with filter)(A) with APEL

Iabc(A) current waveforms of six pulse rectifier with APEL 0

-1

2 0.04 0.042 0.044 0.046 0.048 0.05 0.052 0.054 0.056 0.058

M a g ( % o f F u n d a m e n t a l)
Time (s)

Fundamental (50Hz) = 1.127 , THD= 26.31%

20

15
Iabc(A)

10
0 5

0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order

-2 0.5
Ia(A)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0

time(s) -0.5
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018
Time (s)

Fig.39 source current waveforms of conventional six pulse diode

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 0.5513 , THD= 30.62%

rectifier and six pulse diode rectifier by using APEL 20

15
10
5
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.40 FFT Analysis 41

 CASE 10 : EMULATION OF 12 PULSE RECTIFIER
Iabc.ref(A)
2 2
Ia(without filter)(A)

Iabc(A)
Ia.ref(A) 0
1 Ia(with filter)(A)
-2
Ia(A)

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

0 time(s)
Iabc(without filter)(A)
2
-1

Iabc(A)
0

-2 -2
0.02 0.04 0.06 0.08 0.1 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(s) time(s)
 THD values: 2
Iab(with filter)(A)

(Without filter)APEL 19.46%

Iabc(A)
0

(With filter)APEL 16.29% -2

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(s)
conventional 12.19%

Fig.41 reference current and source current for twelve pulse diode rectifier by using APEL
12/24/2020 S.C.E.T,SURAT 42
 CASE 9 : EMULATION OF 12 PULSE RECTIFIER
Ia(without filter)(A) with APEL
1

(Iabc)Current of 12 pulse diode rectifier -1

0

2 0.04 0.042 0.044 0.046 0.048 0.05 0.052

Time (s)
0.054 0.056 0.058

M a g (% o f F u n d a m e n ta l)
Ia (A) Fundamental (50Hz) = 1.127 , THD= 19.46%
Iabc (A)

Ib (A) 10

0 Ic (A) 5

0
0 5 10 15 20 25 30
Harmonic order
-2
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Ia (with filter)(A) with filter
time (s) 1
0

(Iabc)Current of 12 pulse diode rectifier with APEL

-1
0.04 0.042 0.044 0.046 0.048 0.05 0.052 0.054 0.056 0.058

2 Time (s)

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1.127 , THD= 16.29%

10
Iabc(A)

5
0 0
0 5 10 15 20 25 30
Harmonic order

Ia(A)
-2 1

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0

-1

time(s) 0.02 0.022 0.024 0.026 0.028 0.03

Time (s)
0.032 0.034 0.036 0.038

M a g (% o f F u n d a m e n ta l)
Fundamental (50Hz) = 1.834 , THD= 12.19%
Fig.42 source current waveforms of conventional 12 pulse diode 10

rectifier and 12 pulse diode rectifier by using APEL 5

0
0 5 10 15 20 25 30 35 40
Harmonic order

12/24/2020 S.C.E.T,SURAT Fig.43 FFT Analysis 43

 HARDWARE BLOCKDIAGRAM

AC POWER IGBT POWER

SUPPLY CARD
110V,50Hz

Iabc Vabc IGBT FIRING

CARD

SENSOR
CARD MICRO-
CONTROLLER

CONTROL UNIT

Fig.44 Hardware block diagram

12/24/2020 S.C.E.T,SURAT 44
 HARDWARE DETAILS

 Component list:

Component list Quantity

3-phase 110V AC supply 1
3-phase converter 6-IGBT,1200V/25amp
Infineon driver card 1
AC Sensor card 1
DC capacitor link 2 nos.- 4700μF
Source impedance 3 nos.(0.6mH/5Amp)
Load bank R-load(1 or 3 lamp-100W)

12/24/2020 S.C.E.T,SURAT 45
 HARDWARE DETAILS

 Hardware Requirements

The following sets of hardware cards.

• STM32 Discovery Card

• ARM Cortex M4 - WJ - 32 Bit Kit

• IGBT Driver and Power Card

 Software Requirements

Installation of following software’s is required for the experimentation

• Matlab 2014a

• MDK516a (Kei l ARM IDE)

• STM32 ST-LINK Utility_v2.3.0

• waijung17_02a or higher

12/24/2020 S.C.E.T,SURAT 46
 HARDWARE DETAILS

 Waijung Block Set:

• "Waijung" is a Simulink Block set can be used to easily and automatically generate C code from
MATLAB/Simulink simulation models for many kinds of microcontrollers (Targets).
• Waijung is designed specifically to support STM32F4 family of microcontrollers (STM32F4 Target) which
is a Hi-Performance & DSP MCU from STMicroelectronics.
 The followings list some of features:
• Low-Cost Hi-Performance
• Easily measure execution time of your target in real-time with ease
• GNU Tools for ARM Embedded Processors is built-in Waijung Auto Compile
• No need to install any third party compiler

12/24/2020 S.C.E.T,SURAT 47
 HARDWARE DETAILS

 ARM Cortex M4
• This board is ST Discovery card for STM32F407VGT6
microcontroller.
• 1MB of Flash memory,
• 192 KB of RAM
• Running at 168 MHz
• 3×12-bit,A/D converters: up to 24 channels 2×12-bit D/A
converters
• Waijung compatible

Fig.45 ARM Cortex M4

12/24/2020 S.C.E.T,SURAT 48
 HARDWARE DETAILS

 SENSOR CARD:
• Isolated measurement.
• Three voltage sensing using external PT (Potential
Transformer 230V/6V recommended).
• Per phase 6V, 50 Hz voltage to 0-3V AC.
• Three current sensing using CT (Current Transformer).
• 5 A, 50 Hz current to 0-3V AC.
• Unipolar output with DC offset.
• Can directly connect to ADC.

Fig.46 sensor card

12/24/2020 S.C.E.T,SURAT 49
 HARDWARE DETAILS

 IGBT POWER AND DRIVER CARD

• Suitable for 1200V, 25 A IGBTs, Individual six channel isolated
IGBT driving
• Output pulses: Isolated +16V/-8V
• Shoot through protection
• 6 SMPS for generating +16V/-8V isolated power supplies required for driver IC
• RESET to start gate pulses after clearing the FAULT. Driver can be RESET via
on board
• 6 individual Fault and Ready indications

Fig.47 IGBT power and driver card

12/24/2020 S.C.E.T,SURAT 50
 OPENLOOP HARDWARE BLOCKDIAGRAM

Iabc

Fig.48 Open loop hardware block diagram WAIJUNG MATLAB

BLOCK

12/24/2020 S.C.E.T,SURAT 51
 HARDWARE MODEL

Fig.49 hardware model (open loop)

12/24/2020 S.C.E.T,SURAT 52
 HARDWARE SETUP

Fig.50 hardware model (open loop)

12/24/2020 S.C.E.T,SURAT 53
 HARDWARE RESULTS

Fig.51 hardware result for input voltage Fig.52 hardware result for theta

12/24/2020 S.C.E.T,SURAT 54
 HARDWARE RESULTS

Fig. 53 Hardware result for hysteresis band Fig. 54 Hardware result for gate pulses and input voltage(Vr)

12/24/2020 S.C.E.T,SURAT 55
 HARDWARE RESULTS

Fig. 55 Hardware result of input current (Ir) Fig. 56 Reference current for n=1 and n=5

12/24/2020 S.C.E.T,SURAT 56
 PAPER ACCEPTANCE

 A paper titled as “Simulation Analysis of Active Programmable Electronic AC Load” has

been accepted in 3rd International Conference for Convergence in Technology (I2CT) , IEEE
Conference, Pune.

12/24/2020 S.C.E.T,SURAT 57
 SUMMARY

 Using the AEL load the testing of various sources such as transformer, power supplies etc, can be
done easily providing flexibility to the researchers.
 The control strategy for APEL has demonstrated to be able to emulate different load profiles, e.g.
linear, dynamic linear and non-linear ones. Presented control strategy is based on a three phase
programmable synthesis unit for different sequences and current harmonics.
 The traditional hysteresis current control technique tracks the source current closely the reference
current; though depends upon the band or margins.
 Emulation of different load profiles could be carried out by changing values of currents in
dq0 frame, instead of changing the load directly.
 Simulation results have been carried out to validate the effectiveness of this control structure.

12/24/2020 S.C.E.T,SURAT 58
 FUTURE WORK

 Control strategy has been implemented in open loop.

 Closed loop will be carried out.

12/24/2020 S.C.E.T,SURAT 59
 REFERENCES

[1] Zhi Geng, Gu, Tianqi Hong, Jiaxin Teng, Dariusz Czarkowski ,Novel Control Architecture for Programmable Electronic AC Load to
Achieve Harmonic Load Profiles IEEE Transaction .2017
[2] J. Faiz, G Shahgholian, Modeling and Simulation of a three phase inverters with rectifier type of nonlinear loads in Armenian Journal of
physics, vol. 2, no. 4, pp. 307-316, 2009.
[3] S.Upadhyay, S.Mishra, A.Joshi, A wide bandwidth electronic load, in IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 733–739,Feb.2012.

[4] R. Klein, A. de Paiva and M.Mezaroba,Emulation of nonlinear loads with energy regeneration, IEEE in XI Brazillian Power Electronics
Conference, pp.884-890, Sep.2011.
[5] J. A. Heerdt, D. F. Coutihno, S. A. Mussa and M. L. Heldwein,Control Strategy for Current Harmonic Programmed AC Active Electronic
Power Loads in IEEE Transactions on Industrial Electronics, vol. 61, no. 8, pp.3810-3822, Aug 2014
[6] S. Wang, Z. Hou, and C. Peng, A repetitive control strategy of ac electronic load with energy recycling,in Proc. International Technology
and Innovation Conference (ITIC), pp. 1–4, Oct. 2009
[7] J. W.Baek, M. H. Ryoo, J. Hyun. Kim and Jih-Sheng Lai, 50 kVA regenerative active load for power test system,in Power Electronics and
Applications, EuropeanConference on, Aalborg, pp. 1–8, Sep. 2007.

12/24/2020 S.C.E.T,SURAT 60
 REFERENCES
[8] M. Kesler, E. Ozdemir, M. C. Kisacikoglu and L. M. Tolbert, “Power converter-based three-phase nonlinear load emulator for a
hardware testbed system”, Power Electronics, IEEE Transaction on, On pages (s): 5806-5812, Volume: 29, Issue:11, Nov. 2014.
[9] J.-W. Baek, M.-H. Ryoo, J. H. Kim, and J.-S. Lai, “50kVA Regenerative Active load for power test system,” in European Conference
on Power Electronics and Applications, sept. 2007, pp. 1 –8.
[10] Y. S. Rao and M. Chandorkar, “Electrical load emulation using power electronic converters,” TENCON 2008 - 2008 IEEE Region 10
Conference, Hyderabad, 2008, pp. 1-6.
[11] R. L. Klein, A. F. de Paiva and M. Mezaroba, “Emulation of nonlinear loads with energy regeneration,” XI Brazilian Power
Electronics Conference, Praiamar, 2011, pp. 884-890.
[12] W. Zhang and X. Zhang, “A novel AC electronic load based on hysteresis current control scheme,”2011 International Conference on
Electrical and Control Engineering, Yichang, 2011, pp. 1913-1916.
[13] L. B. Kehler, L. C. Corrêa, C. G. Ribeiro, J. G. Trapp, J. M. Lenz and F. A. Farret, “Electronically adjustable load for testing three
phase AC systems,” 2013 Brazilian Power Electronics Conference, Gramado, 2013, pp. 1082-1087.
[14] X. Fang, Chunjie Li, Zhiqiao Chen and Liangbing Guo, “Z-source converter-based feedback type electronic load,” 2010 IEEE
International Conference on Automation and Logistics, Hong Kong and Macau, 2010, pp. 189-192
[15] J Nagrath, D P Kothari, “Modern Power System Analysis”

12/24/2020 S.C.E.T,SURAT 61