sensors
Article
An Improved Voltage Clamp Circuit Suitable for Accurate
Measurement of the Conduction Loss of Power
Electronic Devices
Qiuping Yu, Zhibin Zhao *, Peng Sun, Bin Zhao and Yumeng Cai






Citation: Yu, Q.; Zhao, Z.; Sun, P.;
Zhao, B.; Cai, Y. An Improved Voltage
Clamp Circuit Suitable for Accurate
Measurement of the Conduction Loss
of Power Electronic Devices. Sensors
2021, 21, 4285. https://doi.org/
10.3390/s21134285
Academic Editor: Toan Phung
Received: 3 June 2021
Accepted: 21 June 2021
Published: 23 June 2021
Publisher’s Note: MDPI stays neutral
with regard to jurisdictional claims in
published maps and institutional affil-
iations.
Copyright: © 2021 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Sensors 2021, 21, 4285. https://doi.org/10.3390/s21134285
State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric
Power University, Beijing 102206, China; yuqiuping@ncepu.edu.cn (Q.Y.); sunpeng@ncepu.edu.cn (P.S.);
binzhao@ncepu.edu.cn (B.Z.); caiyumeng@ncepu.edu.cn (Y.C.)
* Correspondence: zhibinzhao@ncepu.edu.cn
Abstract: Power electronic devices are essential components of high-capacity industrial converters.
Accurate assessment of their power loss, including switching loss and conduction loss, is essential to
improving electrothermal stability. To accurately calculate the conduction loss, a drain–source voltage
clamp circuit is required to measure the on-state voltage. In this paper, the conventional drain–source
voltage clamp circuit based on a transistor is comprehensively investigated by theoretical analysis,
simulations, and experiments. It is demonstrated that the anti-parallel diodes and the gate-shunt
capacitance of the conventional drain–source voltage clamp circuit have adverse impacts on the
accuracy and security of the conduction loss measurement. Based on the above analysis, an improved
drain–source voltage clamp circuit, derived from the conventional drain–source voltage clamp circuit,
is proposed to solve the above problems. The operational advantages, physical structure, and design
guidelines of the improved circuit are fully presented. In addition, to evaluate the influence of
component parameters on circuit performance, this article comprehensively extracts three electrical
quantities as judgment indicators. Based on the working mechanism of the improved circuit and
the indicators mentioned above, general mathematical analysis and derivation are carried out to
give guidelines for component selection. Finally, extensive experiments and detailed analyses are
presented to validate the effectiveness of the proposed drain–source voltage clamp circuit. Compared
with the conventional drain–source voltage clamp circuit, the improved drain–source voltage clamp
circuit has higher measurement accuracy and working security when measuring conduction loss,
and the proposed component selection method is verified to be reasonable and effective for better
utilizing the clamp circuit.
Keywords: power electronic devices; drain–source voltage clamp circuit; power loss; conduction
loss; on-state voltage
1. Introduction
High-voltage, large-capacity power electronic conversion equipment dramatically
improves the transmission capacity of the flexible AC/DC grid as well as the electric trac-
tion control ability [1]. As the voltage withstand ability and switching frequency of power
semiconductor devices continue to increase, and the volume continues to decrease, power
electronic converters have higher efficiency and power density [2–4]. However, converters
face reliability challenges. The overheating failure of the internal power electronic devices
is one of the main reasons for damage to the converter [5–7], and most heat comes from
the power loss of power semiconductor devices. Imprecise power loss measurement will
lead to the wrong design of the thermal management system (TMS), which will affect the
reliability and cause premature failure of the equipment [8,9]. Accurately obtaining the
power loss of the device is a crucial prerequisite for determining the thermal solution,
which will affect the efficiency, cost, and power density of the entire system.
https://www.mdpi.com/journal/sensors
Sensors 2021, 21, 4285 2 of 19

Common methods for obtaining power loss are calorimetry [10,11], building a physical
model [12,13], establishing a loss look-up table or fitting power loss as a function [14,15],
and directly integrating the product of the square of the on-state current root mean square
and the on-state resistance [16]. However, the above methods often introduce significant
errors due to model or measurement problems.
At present, an accurate way to calculate power loss, including switching loss and
conduction loss, is to measure the on-state drain–source voltage (vds_on ) across the device
and the current (id ) flowing through the device and then integrate their product. How-
ever, when calculating the conduction loss, it is difficult to measure the on-state voltage
accurately. It is directly related to the operating characteristics of the power semiconductor
device that frequently converts between the on state and the off state. The off-state drain–
source voltage (vds_off ) can reach hundreds or thousands of volts, while the on-state voltage
vds_on is only a few volts [17], making it challenging to select a suitable oscilloscope range.
An excessive range will lead to a significant error in the on-state voltage measurement, and
more seriously, the measurement result may be negative due to the influence of noise. If
the oscilloscope range is set too small, the “oscilloscope saturation” phenomenon will be
seen [18].
The drain–source voltage clamp circuit (DVCC) is frequently used to measure the
on-state voltage vds_on by clamping the off-state voltage of the device under test (DUT)
to a lower value. In existing research, six types of DVCCs have been proposed for the
measurement of vds_on . The DVCC proposed in [19,20] clamps the off-state voltage of
the DUT by using the high-voltage breakdown characteristics of the Zener diode. It is
simple to implement. However, its measurement error due to the leakage current of the
Zener diode and its measurement delay due to the resistance–capacitance (RC) loop limit
its further application. Gelagaev [18] analyzed the DVCC based on a current mirror in
detail, and this circuit solved the problem of measurement delay. However, it has been
shown that since the output currents on both sides of the current mirror cannot be entirely
consistent, the current flowing through the diodes on both sides may be different, which
may cause measurement errors. Furthermore, in [21], a DVCC based on one diode is
described. The forward voltage of its diode is affected by temperature and current, leading
to cumbersome corrections for vds_on . This problem was resolved in [22,23]. The DVCC
proposed in [22,23] introduced two diodes and a proportional amplifier circuit to improve
measurement accuracy. However, due to the difference in the physical positions and
forward current of the two diodes, it is difficult to ensure that the voltage drop of the
two diodes is equal, which may lead to inaccurate results. Yu et al. [24] presented an
innovative design for the DVCC with improved real-time measurement accuracy. Guacci
et al. described a DVCC in [25], which can accurately correct the voltage offset caused
by the diode voltage drop and has a higher measurement accuracy. Both of these circuits
in [24,25] introduce operational amplifiers, which increases the complexity of the course. A
DVCC integrated with a half-bridge circuit was employed in [26] for device evaluation in
the hard-switching test and the soft-switching conditions. However, this DVCC ignores
the influence of diode leakage current on the on-state voltage measurement, and there may
be measurement errors. The DVCC based on the transistor is analyzed in [27]. It avoids
most of the problems mentioned earlier. However, the gate–source spike voltage due to the
instantaneous high current of the transistor gate resistance may damage the DVCC itself.
Additionally, the purpose of designing this circuit is to measure on-state resistance Rds_on ,
and it is not suitable for conduction loss measurement.
In summary, these existing DVCCs, in terms of measurement accuracy, work com-
plexity, and design aim, cannot be used for conduction loss (Ploss_on ) measurement of
power semiconductor devices. Therefore, this paper concerns the drawbacks of the conven-
tional DVCC based on the transistor (hereinafter referred to as “conventional DVCC”) and
proposes an improved DVCC (hereinafter referred to as “improved DVCC”) architecture
suitable for the Ploss_on measurement. The new circuit is derived from the conventional
DVCC. The remainder of this paper is organized as follows. In Section 2, the circuit struc-
Sensors 2021, 21, 4285 3 of 19

ture, work principle, and drawbacks of the conventional DVCC are analyzed in detail. Then,
the schematic and the advantages of the improved DVCC are presented. Furthermore, the
influence of the components’ parameters on the circuit performance of the improved DVCC
is analyzed in Section 3. Here, component selection guidelines are also given. In Section 4,
the measurement accuracy and work security improvement of the improved DVCC are
verified through simulated and experimental comparisons with the conventional DVCC.
Simultaneously, the effectiveness of the selection theory is also investigated and proven.
Finally, Section 5 concludes this paper.

2. Design of the Improved DVCC

Compared with the existing DVCCs, which are mainly applied to the on-state resis-
tance measurement of the DUT, more problems need to be considered when designing a
DVCC suitable for conduction loss measurement. After the DUT is turned on, it will go
through two typical states, enter the oscillation state (on-oscillation state), and gradually
reach steady state (on-steady state). The measurement results of these existing DVCCs can
well reflect the on-state voltage vds_on_ste when the DUT is in the on-steady state. However,
when measuring the conduction loss, in addition to the above-mentioned on-steady state
voltage, the DVCC must be able to accurately measure the on-state voltage vds_on_osc when
the DUT is in the on-oscillation state. Any error at any stage will cause errors in the
calculation of the device conduction loss.
In addition, many common problems need to be avoided in both on-state resistance
and conduction loss measurement. First of all, the DVCCs cannot have measurement
delays. Once the voltage data lag or lead the current data, errors will occur in the loss
integral calculation. Secondly, power electronic devices, such as diodes, metal–oxide–
semiconductor field–effect transistors (MOSFET), etc., are often introduced into DVCCs
to realize the voltage clamping function. Due to the faster switching speed and higher
operating voltage of the DUT, it is easy to make these auxiliary devices out of safe working
conditions. Therefore, when designing a DVCC, it is necessary to focus on the security of
these auxiliary devices.

2.1. The Structure and Working Principle of the Conventional DVCC

The schematic diagram of the conventional DVCC is shown in Figure 1. The auxiliary
device MOSFET (M) is used to withstand the high off-state voltage of the DUT, thereby
limiting the potential of the voltage measurement point A. The DC voltage supply V cc and
the gate resistor R2 are located at the gate of M, and together with the resistor R3 , they
control the turn-on and turn-off of M. The D and S terminals of the circuit are connected
to the drain and source of the DUT, respectively, while the A and B terminals are used
Sensors 2021, 21, x FOR PEER REVIEW 4 ofto
19
measure output voltage (vout ).

M
D A
-
vgs_M
+
D1 D3

R2 i2 i3
C0 D2 R3
Vcc
S B

Figure1.1. The
Figure The schematic
schematicdiagram
diagramof
ofthe
theconventional
conventionalDVCC.
DVCC.

When the of
2.2. Drawbacks DUT DVCCD3 is broken down, causing the current flowing
is in the off-state,
the Conventional
through R3 toof
In view increase
the factsharply.
that theAt this time,
purpose theconventional
of the source potential
DVCCof Mis rises, and the
to measure gate-
the on-
source voltage vgs_M decreases. When v gs_M is less than the threshold voltage V
state resistance, when it is applied to conduction loss measurement, there are some severe th_M of M,
M is turned off and shares most of the off-state voltage, limiting
problems, which are further discussed in the following subsections. v out to a small voltage

2.2.1. Low Measurement Accuracy

To reduce the voltage negative overshoot between A and B when the DUT is turned
on, the conventional DVCC connects the diodes D1 and D2 in reverse parallel between the
Sensors 2021, 21, 4285 4 of 19

value. When the DUT is turned on, the source potential of M decreases, causing the vgs_M
to become higher than V th_M , bringing the M into conduction. As a result, vout is equal to
vds_on .

2.2. Drawbacks of the Conventional DVCC

In view of the fact that the purpose of the conventional DVCC is to measure the
on-state resistance, when it is applied to conduction loss measurement, there are some
severe problems, which are further discussed in the following subsections.

2.2.1. Low Measurement Accuracy

To reduce the voltage negative overshoot between A and B when the DUT is turned
on, the conventional DVCC connects the diodes D1 and D2 in reverse parallel between the
measurement points A and B and utilizes their unidirectional conductivity characteristics
to eliminate the voltage overshoot.
Assume that the forward voltage drops of diodes are V D1 and V D2 , respectively.
During the on-oscillation state, if vds_on_osc is greater than −(V D1 + V D2 ), D1 and D2 are
reversely cut off. Therefore, vout = vds_on_osc . Once vds_on_osc is less than −(V D1 + V D2 ), D1
and D2 will immediately switch to the forward conduction state, and the output voltage
will remain unchanged at −(V D1 + V D2 ), resulting in vout 6= vds_on . The two diodes limit the
negative voltage overshoot and do not affect the on-state resistance measurement. However,
when measuring the conduction loss, the loss during oscillation cannot be ignored [28].
The conventional DVCC cannot measure vds_on_osc accurately nor can it accurately measure
the conduction loss.

2.2.2. Low Working Security

To reduce the current flowing through the DC voltage supply (V cc ) and ensure the
safety of V cc , the conventional DVCC shown in Figure 1 has a capacitor C0 connected
in parallel to the gate of M [22]. However, the existence of C0 seriously affects the work
security of auxiliary device M. When the DUT is turned off, the drain–source voltage
vds and the current on R3 increases sharply, which will cause an instantaneous negative
overshoot V gs_M(max) at the gate–source of M. If V gs_M(max) exceeds the gate−source voltage
withstand limit of M (V gs_limit ), M will be burned. If negative overshoot V gs_M(max) occurs
at time t0 , the gate−source voltage vgs_M of M will be a negative value in the time interval
[t0 − ∆t, t0 + ∆t]. According to Figure 1, it can be known from KVL that during this period,
vgs_M can be written as in Equation (1), and V gs_M(max) = vgs_M (t0 ):

vgs_M = V cc +i2 R2 − VD3 − i3 R3 , (1)

where V D3 is the breakdown voltage of Zener diode D3 ; i2 and i3 are the current flowing
through R2 and R3 , respectively.
Adding C0 to the gate of M will reduce i2 (t0 ), which can protect V cc . However, since
V gs_M(max) is negative, the decrease in i2 (t0 ) will cause the absolute value of V gs_M(max)
to increase significantly, which will endanger the safety of the MOSFET. In contrast, the
impulse current withstand capability of the widely used DC voltage supply can reach
several amperes or tens of amperes. Even without C0 , i2 (t0 ) is not enough to cause harm to
V cc . Therefore, the benefit of C0 is far less than the harm it causes.

2.3. Proposal of the Improved DVCC

The schematic of the improved DVCC for conduction loss measurement is described
in Figure 2. By conducting two changes in the structure of the conventional DVCC, the
problems existing in the conventional DVCC are solved.
 2.3. Proposal of the Improved DVCC
Sensors 2021, 21, 4285 The schematic of the improved DVCC for conduction loss measurement is described
5 of 19
in Figure 2. By conducting two changes in the structure of the conventional DVCC, the
problems existing in the conventional DVCC are solved.

D M A
-
vgs_M
+ D3

i2 R2 i3
R3
Vcc
S B
Figure 2.
Figure 2. The
The schematic
schematic diagram
diagram of
of the
the improved
improved DVCC.
DVCC.

Firstly, to
Firstly, to accurately
accuratelymeasure measurevvds_on_osc of the DUT, the improved DVCC removes anti-
ds_on_osc of the DUT, the improved DVCC removes
parallel diodes (i.e., D and D in
anti-parallel diodes (i.e., D1 and D2 in Figure
1 2 Figure 1) from1) the
from output voltage
the output measurement
voltage point.
measurement
Under this arrangement, the on-state voltage of the two stages, on-steady
point. Under this arrangement, the on-state voltage of the two stages, on-steady state and state and on-
oscillation state,
on-oscillation both
state, have
both havehigh measurement
high measurement accuracy.
accuracy.Furthermore,
Furthermore,thethe
calculation er-
calculation
ror ofof
error conduction
conduction loss
lossisislimited
limitedtotoa asmall
smallvalue.
value.
In addition,
addition, considering
consideringthe theharmfulness
harmfulness of of
C0 to
C0theto core device
the core M, another
device improve-
M, another im-
ment is to remove
provement the gate-shunt
is to remove the gate-shuntcapacitance (i.e., C0 (i.e.,
capacitance in Figure
C0 in1). This measure
Figure dramati-
1). This measure
cally improves
dramatically the operating
improves the operatingenvironment of M. Inofaddition,
environment there isthere
M. In addition, no need
is notoneed
worryto
about about
worry the safety of Vccof. V
the safety Forcc . typical DCDC
For typical sources,
sources, their
theirimpulse
impulsecurrent
current tolerance often
tolerance often
reaches
reaches several
several amps
amps or or tens
tens of of amps,
amps,while
whilethe
themaximum
maximumcurrent currentflowing throughVVcccc is
flowingthrough is
usually hundreds
hundreds of of milliamps.
milliamps. Therefore,
Therefore, the
the work
work safety
safety ofof VVcc will not
cc will not be
be threatened.
threatened.

3.
3. Component
Component Selection
Selection
In
In Section 2,the
Section 2, thepros ofof
pros thethe
improved
improved DVCC andand
DVCC the cons of conventional
the cons DVCCDVCC
of conventional were
highlighted. In thisIn
were highlighted. section, the influence
this section, of component
the influence parameters
of component on the performance
parameters of
on the perfor-
the improved DVCC is analyzed in detail. Furthermore, guidelines for component
mance of the improved DVCC is analyzed in detail. Furthermore, guidelines for compo- selection
are
nentgiven to utilize
selection the improved
are given to utilizecircuit better. circuit better.
the improved
3.1. Evaluation Indicators
3.1. Evaluation Indicators
Theoretically, there are three conditions that the circuit must meet to perform the
Theoretically, there are three conditions that the circuit must meet to perform the
functions of clamping and measuring normally, as listed below.
functions of clamping and measuring normally, as listed below.
1. Ensure the security of core MOSFET (M);
1. Ensure the security of core MOSFET (M);
2. M should be in the proper working state when the DUT is in the on-state;
2. M should be in the proper working state when the DUT is in the on-state;
3. M should be in the proper working state when the DUT is in the off-state.
3. M should be in the proper working state when the DUT is in the off-state.
Considering
Considering the
the above
above three
three restrictions,
restrictions, this
this article
article comprehensively
comprehensively extracts
extracts three
three
electrical quantities as the judgment indicators of the circuit performance to guide
electrical quantities as the judgment indicators of the circuit performance to guide compo-
com-
nent
ponentselection:
selection:
1.
1. Gate−sourcevoltage
Gate−source voltagenegative
negativeovershoot
overshoot(V
(V ) of)M,
gs_M(max)
gs_M(max)
of M, which
which is denoted
is denoted as1.EI
as EI As1.
As indicated in Section 2, it is necessary to avoid V gs_M(max) exceeding the gate–
indicated in Section 2, it is necessary to avoid Vgs_M(max) exceeding the gate–source tol-
source tolerance of core M. Therefore, the low EI value is of greater significance for
erance of core M. Therefore, the low EI1 value is of1 greater significance for improving
improving the security of M.
the security of M.
2. Gate−source voltage of M (vgs_M(on) ) when the DUT is in the on-state, which is
2. Gate−source voltage of M (vgs_M(on) ) when the DUT is in the on-state, which is denoted
denoted as EI2 . If the DUT is in the on-state, M should also be in the on-state to satisfy
as EI2. If the DUT is in the on-state, M should also be in the on-state to satisfy vout =
vout = vds_on . Therefore, the second evaluation indicator should meet EI2 > V th_M .
vds_on. Therefore, the second evaluation indicator should meet EI2 > Vth_M.
3. Gate−source voltage of M (vgs_M(off) ) when the DUT is in the off-state, which is
3. Gate−source voltage of M (vgs_M(off) ) when the DUT is in the off-state, which is denoted
denoted as EI3 . When the DUT is in the off-state, the working state of M should also
as EI3. When the DUT is in the off-state, the working state of M should also be con-
be consistent with the DUT to withstand high off-voltage and reduce the potential
sistent with the DUT to withstand high off-voltage and reduce the potential of the
of the measurement point A. Under this condition, EI3 should be less than V th_M , so
that M can be turned off reliably [29].
Sensors 2021, 21, 4285 6 of 19

3.2. Selection of MOSFET

Since the parameters of M are closely related to the safe operation of the entire
circuit, criteria for selecting the subject are proposed based on the working principle of the
improved DVCC.
As stated before, with the transitions of DUT from the on-state to the off-state, M also
changes its state rapidly so as to prevent the continuous increase of the source current
of M and prevent EI1 from being too large. Similarly, when the DUT changes from the
off-state to the on-state, M needs to be turned on immediately to avoid measurement delay.
Therefore, it is recommended that the switching speed of M be consistent with or faster
than DUT, which is the first criterion for the selection of M.
In addition, since the improved DVCC utilizes the high blocking voltage characteristic
of M to exercise the clamping function, during the off-state of the DUT, the drain–source
withstand voltage of M is almost the same as that of the DUT. To increase the operational
reliability of M, it is advised that the blocking voltage level of M is consistent with or higher
than the DUT, which is considered the second criterion.

3.3. Selection of DC Voltage Supply Vcc and Zener Diode Breakdown Voltage VD3
3.3.1. Selection Principle of V D3
Since Zener diode D3 is in the gate−source loop of M, EI1 is one of the vital evaluation
indicators for selecting V D3 . The influence of V D3 on the work security of M is analyzed in
this subsection.
According to Figure 2, the gate−source negative overshoot of M can be expressed as
follows:
EI 1 = V cc + I 2 R2 − VD3 − I3 R3 , (2)
where I2 and I3 are the currents flowing through R2 and R3 at time t0 , respectively.
According to Equation (2), V D3 increases, and the absolute value of EI1 increases
accordingly. Based on the interpretation content of the first evaluation indicator, for high
security of M, V D3 should be as small as possible.

3.3.2. Voltage Constraint for Effective Work

The DC voltage supply V cc and the Zener diode D3 jointly control the turn-on and
turn-off of M to make it follow the steps of the state change of DUT. Therefore, it can be
seen that the values of vgs_M(on) and vgs_M(off) are closely related to V cc and V D3 . Based on
the supplementary content when the second and third evaluation indicators are proposed,
it can be estimated that V cc and V D3 have a mutually restrictive relationship. In this paper,
this specific constraint is called the “voltage constraint for effective work (VCEW)” and is
further discussed in the subsequent sections.
When the DUT is in the on-state, EI2 can be expressed as in the equation below:

EI 2 = V cc +i2_on R2 − vds_on , (3)

where i2_on is the current flowing through the resistor R2 when the DUT is in the on-state.
Since M is also in the on-state, i2_on can be obtained as follows:

i2_on = ig_M ≈ 0, (4)

where ig_M is the gate current of M.

Therefore, Equation (3) can be simplified to

EI 2 = V cc − vds_on . (5)

If the working condition of the DUT is known, the maximum on-state voltage V on_max
of the DUT is determined. At this time, the size of EI2 depends on the value of the DC
Sensors 2021, 21, 4285 7 of 19

voltage supply (V cc ). To ensure that M is in the on-state, it should meet the following
condition:
Vcc > V on_max +V th_M . (6)
When the DUT is in the off-state, EI3 can be described as follows:

EI 3 = V cc +i2_off R2 − VD3 0 − i3_off R3 , (7)

where i2_off and i3_off are the currents flowing through R2 and R3 , respectively, when the
DUT is in the off-state; V D3 0 is the voltage across the Zener diode D3 .
Since M is in the off-state, i2_off and i3_off can be obtained as follows:

i3_off = ileak_M ≈ 0, (8)

i2_off = ig_M ≈ 0, (9)

where ileak_M is the leakage current of M.
Equation (7) is further simplified to

EI 3 = V cc −V D3 0 . (10)

When the DUT is in the off-state, D3 has two possible scenarios [30]. If the leakage
current of D3 is more significant than M, D3 is in the reverse cut-off state, and V D3 0 meets
the condition:
VD3 0 ≤ V D3 . (11)
In this scenario, a voltage equilibrium will be established: as V cc changes, V D3 0 changes
accordingly, so that EI3 is always maintained at a voltage less than V th_M . According to
Equation (11), when selecting V cc , its value should satisfy the following condition:

Vcc − VD3 < V th_M . (12)

In another scenario, if the leakage current of D3 is less than M, D3 is in the breakdown

state and V D3 0 = V D3 . Obviously, in this circumstance, V cc is selected based on the below
equation:
EI 3 = V cc − VD3 < V th_M . (13)
Considering Equations (6), (12), and (13) and adding in a margin of error, Equation (14)
is written to reveal the mechanism of VCEW.

Vcc > V on_max +V th_M
. (14)
Vcc −V D3 < 0

3.4. Selection of Gate Resistance R2 and Source Resistance R3

3.4.1. Selection Principle of R2 and R3
R2 and R3 are located in different branches of the gate−source loop of M, so that they
have the opposite effect on EI1 (V gs_M(max) ). Therefore, by choosing appropriate R2 and R3
values, the gate−source voltage negative overshoot (V gs_M(max) ) of M can be suppressed as
much as possible.
At t0 , when the V gs_M(max) occurs, M has been completely turned off, and the improved
DVCC can be equivalent to the course shown in Figure 3 [29].
Sensors 2021, 21, 4285 8 of 19
Sensors 2021, 21, x FOR PEER REVIEW 8 of 19

Cd Cs
D
Id_M Cg D3

I2 R2 I 3
R3
Vcc
S

Figure 3.
Figure 3. Equivalent
Equivalent circuit
circuit of
of the
the improved
improved DVCC.
DVCC.

According to
to Figure
Figure 3,
3, the
the first
first evaluation
evaluation indicator
indicator can
can be
be expressed
expressedas
as
a(b-jc)
EI1 =Vcc − VD3a+(b − jcId_M ) , (15)
EI 1 = V cc − VD3 + b22 +c2 2 Id_M , (15)
b +c
a = R2 Cg − R3 Cs ,
, s,

 a = Rb2=CC g g−+RC3sC (16)
c = wCb= s CC gRg2++CwC s , s Cg R3 , (16)
c = wCs Cg R2 +wCs Cg R3 ,

where Id_M is the drain current of M.
where Id_M is thetodrain
According [29], current of M.Cg << Cs. The coefficient of the third term in Equation
at this time,
(15) is abbreviated as e + jf. Then, C
According to [29], at this time, g <<
the Cs .and
real Theimaginary
coefficient of the of
parts third
EI1term in Equation
can be (15)
written as in
is abbreviated
Equations as e (18),
(17) and + jf. respectively;
Then, the real and imaginary parts of EI1 can be written as in
Equations (17) and (18), respectively;
Re ( EI1 ) = eId_M + |Vcc − VD3 |, (17)
Re( EI 1 ) =|eI d_M | + |Vcc − VD3 |, (17)
Im ( EI1 ) = j fId_M , (18)
 
Im( EI 1(R) 2= j3fCIs)(C
Cg -R s +Cg, )
 (18)
 |e| = (Cg +Cs)2 +(wCs Cg R2+wCs Cg R3
)2 ,
d_M
 (19)
( R Cg − R3 Cs )(C s +CCg R )
 
|e| =  f = (R222Cg-R3Cs)(wCsCg R2+wC
 
s g 3 , (19)
 (C +Cs(C ) +( +wC . 2 (20)
+C )wC +(wCCCg R C Rs C) gR ) 
2 2
g g s ss R +wCg 22 s g 3 3

Since the parasitic capacitance of MOSFET is pF level (10−12),and the oscillation fre-
 
 ( R 2 Cg − R3 Cs )(wC s Cg R2 +wCs Cg R3 ) 

quency of drain current
| f | is=generally
 MHz level (106~108). Therefore, . (Cg + Cs) >> (wCsCgR2
(20)
2 2 
( C + C ) +( wC C R + wC C R )

+ wCsCgR3). Based on this, Equations
 g s(21) and (22)
s g can
2 be sderived;
g 3

Since the parasitic capacitance of MOSFET |e| ≫ f ,is pF level (10−12 ), and the oscillation (21)
frequency of drain current is generally MHz level (10 6 ~108 ). Therefore, (C + C ) >>
(R2 Cg -R3 Cs )(Cs +Cg ) R3 Cs -R2 Cg g s
|EIon
(wCs Cg R2 + wCs Cg R3 ). Based 1 | ≈this,
|e| ≈Equations (21)
2 and= (22) can.be derived; (22)
(C +C ) g s Cg +Cs

|  |f|, correlated with R3 and negatively (21)

According to Equation (22), |EI1| is|epositively cor-
related with R2. Therefore, the selection
 guide for these two resistors is to increase R2 and
decrease R3 as much as possible.  ( RIt2 C
isgworth
− R3 Cs noting
)(C s +Cthat
g  this
R3increase
Cs − R2 Cor
g decrease is not


unlimited, which ≈ |e| ≈ in more detail in the
| EIis1 |described  =
following subsection. . (22)
( C g + C s )2 Cg +Cs

 
3.4.2.According
Measurement Error Constraint
to Equation (22), |EI1 | is positively correlated with R3 and negatively
correlated with R . Therefore,
During the on-oscillation
2 the selection
state, with R3guide for these
decreasing, thetwo resistors isaccuracy
measurement to increase R2
of the
and decrease R
on-state voltage as much as possible. It is worth noting that this increase or decrease
3 vds_on_osc gradually decreases. To make the relative error of the vds_on_osc is not
unlimited,
measurementwhich
lessisthan
described
r%, R3 in more be
cannot detail
too in the following
small. This papersubsection.
refers to this constraint re-
lationship as the “measurement error constraint” (MEC).
3.4.2. Measurement Error Constraint
During the on-oscillation state, vds_on_osc can be described as follows:
During the on-oscillation state, with R3 decreasing, the measurement accuracy of the
on-state voltage vds_on_osc graduallyvdecreases.
ds_on_osc = vTo +vout,the relative error of the v
make
ds_M (23)
ds_on_osc
measurement
where vds_M is the than r%, R3 cannot
lessdrain–source voltage be too small. This paper refers to this constraint
of M.
relationship as the “measurement error constraint” (MEC).
Sensors 2021, 21, 4285 9 of 19

During the on-oscillation state, vds_on_osc can be described as follows:

vds_on_osc = vds_M +vout , (23)

where vds_M is the drain–source voltage of M.

During this process, vds_on_osc gradually shifts from the on-oscillation state to the
on-steady state in the form of a second-order oscillation. According to the structure of the
improved DVCC, D3 is connected in reverse between A and B. Therefore, when vds_on_osc >
0, D3 is in the reverse cut-off state, and vout can be expressed as follows:

RD3_off + R3
vout = vds_on_osc × , (24)
RD3_off + R3 + Rds_M

where RD3_off is the equivalent resistance of D3 when it is in the reverse cut-off state; Rds_M
is the equivalent resistance of M.
Since M has been fully turned on at this stage, Rds_M has the same value as the on-state
resistance of M. In addition, considering that D3 can be regarded as an open circuit at this
time, the relationship between vout and vds_on_osc can be expressed as follows:

vout ≈ vds_on_osc . (25)

However, when vds_on_osc < 0, D3 is in the forward conduction state, and vout can be
expressed as follows:

RD3_on + R3
vout = vds_on_osc × , (26)
RD3_on + R3 + Rds_M

where RD3_on is the equivalent resistance of D3 when it is in the forward conduction state.
In this case, it is essential that the resistance of R3 not be too small, so that the
measurement accuracy is not compromised due to the partial voltage of Rds_M . Therefore,
restricted by MEC, R3 needs to meet the following condition:

RD3_on + R3
vds_on_osc ×(1 − ) < vds_on_osc ×r%. (27)
RD3_on + R3 + Rds_M

Furthermore, Equation (27) is simplified to

1 − r%
R3 > Rds_M × ( ) − RD3_on , (28)
r%
where r% is generally around 5%.

3.4.3. Switching Speed Constraint

R2 is located at the gate of M. Therefore, when R2 increases, the gate charging and
discharging speed of the gate driver are slowed down accordingly [29]. In an attempt to
ensure that the switching speed of M is not slower than that of the DUT, R2 cannot be too
large. This paper calls this constraint relationship the “switching speed constraint” (SSC).
In order to obtain the limit of R2 , the influence of R2 on the rising speed of vgs_M
is simplified as the influence of R2 on the charging time constant when M is turned on.
According to Equations (5) and (10), when M is turned on, the amount of change in vgs_M
is ((V cc − vds_on ) − (V cc − V D3 0 )).
Therefore, restricted by SSC, R2 needs to meet the following condition:

(V cc −vds_on ) − (V cc −V D3 0 ) Vg_max −V th_DUT

< , (29)
A B
Sensors 2021, 21, 4285 10 of 19

A = R2 C1gs_M
(
1 (30)
B = Rg Cgs_DUT

where V g_max is the gate−source voltage stability value of the DUT; Rg and V th_DUT are
the gate drive resistance and the threshold voltage of the DUT, respectively; and Cgs_M and
Cgs_DUT are the gate−source parasitic capacitances of M and DUT, respectively.
Considering that V D3 0 ≤ V D3 , Equation (30) can be further simplified to

Rg Cgs_DUT (V g_max −V th_DUT
Sensors 2021, 21, x FOR PEER REVIEW R2 < . (31)
10 of 19
Cgs_M ((V cc −vds_on ) − (V cc −V D3 ))

4. Simulation and Experimental Verification

4. Simulation and Experimental Verification
This paper set up a test platform integrating conventional DVCC and improved
DVCC,This paper in
as shown setFigure
up a test
4, toplatform
evaluate integrating conventional
the measurement accuracy DVCC and improved
and work safety of the
improved DVCC and the correctness of the selection theory. The primary work
DVCC, as shown in Figure 4, to evaluate the measurement accuracy and circuitsafety
of theoftest
the improved DVCC and the correctness of the selection theory. The primary circuit of the
platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode D0 ,
test platform is a double pulse test circuit (DPTC), including a DUT, freewheeling diode
bus capacitor Cbus , digital signal processing (DSP), and drive module V g . DSP is used to
D0, bus capacitor Cbus, digital signal processing (DSP), and drive module Vg. DSP is used
transmit drive signals to control the turn-on and turn-off of the DUT.
to transmit drive signals to control the turn-on and turn-off of the DUT.
The voltage clamp circuit comprises a MOSFET (M), DC source V cc , gate resistance
The voltage clamp circuit comprises a MOSFET (M), DC source Vcc, gate resistance
R2 , source resistance R3 , and Zener diode D3 . In order to facilitate the comparison between
R2, source resistance R3, and Zener diode D3. In order to facilitate the comparison between
the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor
the improved DVCC and conventional DVCC, the connectors for the gate-shunt capacitor
C0C0and the anti-parallel diodes D and D are reserved.
and the anti-parallel diodes D11and D2 2are reserved.

Bus capacitor Freewheeling diode

DUT
Driver module

CDVCC and
NDVCC
DSP

(a) (b) (c)

Figure 4. Test platform. (a) Test platform overview; (b) DVCC section; (c) gate driver.
Figure 4. Test platform. (a) Test platform overview; (b) DVCC section; (c) gate driver.

Thespecific
The specific experimental
experimentalconditions
conditionsareare
listed in Table
listed 1. Both
in Table 1. the
BothDUT
theand
DUT theand
aux-the
iliary device M are the 1200 V/31.6 A SiC MOSFET produced by CREE,
auxiliary device M are the 1200 V/31.6 A SiC MOSFET produced by CREE, while the while the free-
wheeling diode D0 is the SiC Schottky diode of the unified manufacturer.
freewheeling diode D0 is the SiC Schottky diode of the unified manufacturer.
Table 1. Test conditions.
Table 1. Test conditions.
Parameters Value
VDCParameters 400 V/500 V Value
Cbus V DC 200 μF400 V/500 V
Lload Cbus 0.7 mH 200 µF
Lload 0.7 mH
Vg +20 V/−5 V
Vg +20 V/−5 V
According to the experimental platform shown in Figure 4, the corresponding equiv-
alent simulation circuit is extracted, as shown in Figure 5. Inside the dotted frame on the
right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its
circuit components are shown in Table 2. The simulation models of DUT, M, and D0 are
all from the semiconductor company that produces the device, and the parasitic parame-
ters are extracted by finite element simulation software.

Table 2. Circuit parameter index.

Symbol Parameters
Lg1 Parasitic inductance of the gate of the DUT
Sensors 2021, 21, 4285 11 of 19

According to the experimental platform shown in Figure 4, the corresponding equiva-

lent simulation circuit is extracted, as shown in Figure 5. Inside the dotted frame on the
right is the DVCC, while the double pulse circuit is in the dotted frame on the left, and its
circuit components are shown in Table 2. The simulation models of DUT, M, and D0 are all
from the semiconductor company that produces the device, and the parasitic parameters
are extracted by finite element simulation software.

Table 2. Circuit parameter index.

Symbol Parameters
Lg1 Parasitic inductance of the gate of the DUT
Ld1 Parasitic inductance of the drain of the DUT
Sensors 2021, 21, x FOR PEER REVIEW 11 of 19
Ls1 Parasitic inductance of the source of the DUT
Rd1 Parasitic resistance of the drain of the DUT
Rs1 Parasitic resistance of the source of the DUT
Rg Gate drive resistance of the DUT
D0 Freewheeling diode
D0 Freewheeling diode
VDC V DC Bus voltage
Bus voltage

DPTC

Lload Rd1
CF
Ld1 DVCC
D0 M A
VDC Cbus DUT
Rg Lg1 D1 D3
R2
D2 R3
C0
Vg Vcc
Rs1 B
Ls1

Figure 5. Equivalent simulation circuit.

Figure 5. Equivalent simulation circuit.
4.1. Conduction
4.1. Conduction Loss
Loss Measurement
Measurement Accuracy
Accuracy
4.1.1. Quantitative Simulation Analysis
4.1.1. Quantitative Simulation Analysis
Since the oscilloscope cannot measure the accurate value of the on-state voltage vds_on ,
Sinceto
it is hard thequantitatively
oscilloscope cannot
analyzemeasure the accurate
the relative value of the
error between theon-state
output voltage
voltagevvds_on ,
out
it is hard to quantitatively analyze the relative error between the output voltage
and vds_on through experiments. Therefore, this work uses the simulation circuit shown vout and

vds_on
in through
Figure experiments.
5 to compare Therefore,
the on-state this work
voltage and uses the simulation
conduction circuit shown
loss measurement in Fig-
accuracy
ure 5 to compare
between the on-state
the conventional DVCCvoltage
andand conductionDVCC.
the improved loss measurement accuracy
Under the working between
condition
the conventional
that DVCC
V DC is set to 500 andsimulation
V, the the improved DVCC.
results Underinthe
are shown working
Figure 6. condition that VDC
is set to 500V, the simulation results are shown in Figure 6.

900 900
vout vds Conventional DVCC vout vds Improved DVCC

600 600
vds(V)

vds(V)

300 300

On−oscillation state On−steady state On−oscillation state On−steady state

0 0

8 10 12 14 8 10 12 14
time(μs) time(μs)
(a) (b)
40 40
vout vds Conventional DVCC vout vds Improved DVCC
Sensors 2021, 21, 4285 12 of 19
Sensors 2021, 21, x FOR PEER REVIEW 12 of 20

900 900
vout vds Conventional DVCC vout vds Improved DVCC

600 600
vds(V)

vds(V)
300 300

On−oscillation state On−steady state On−oscillation state On−steady state

0 0

8 10 12 14 8 10 12 14
time(μs) time(μs)
(a) (b)
40 40
vout vds Conventional DVCC vout vds Improved DVCC

20 20
vds(V)

0 vds(V) 0

T1 T2 T3 T1 T2 T3
-20 -20
11.55 11.60 11.65 11.70 11.75 11.55 11.60 11.65 11.70 11.75
time(μs) time(μs)
(c) (d)

3.0 3.0
vout vds Conventional DVCC vout vds Improved DVCC
2.5 2.5
vds(V)

vds(V)

2.0 2.0

1.5 T5 1.5
T4 T6 T4 T5 T6

1.0
12.0 12.2 12.4 12.6 1.0
time(μs) 12.0 12.2 12.4 12.6
time(μs)
(e) (f)
Figure 6. vout and vds waveform comparison. (a) Waveform overview of the conventional DVCC; (b) waveform overview
Figure 6. vout and vds waveform comparison. (a) Waveform overview of the conventional DVCC; (b) waveform overview of
of the improved DVCC; (c) waveform of the conventional DVCC during the on-oscillation state; (d) waveform of the
the improved
improved DVCC;
DVCC (c) waveform
during of the conventional
the on-oscillation DVCC during
state; (e) waveform the on-oscillation
of the conventional DVCC state; (d) waveform
during of the
the on-steady improved
state; (f)
DVCC during
waveform of the on-oscillation
the improved DVCCstate; (e) waveform
during of the
the on-steady conventional DVCC during the on-steady state; (f) waveform of
state.
the improved DVCC during the on-steady state.
In Figure 6, vds is the voltage waveform measured directly at the drain and source of
In Figure
the DUT. When6,the vdsDUT
is the voltage
is in the on waveform
state, vds = vmeasured
ds_on. As showndirectly at the6c,
in Figure drain and source
the conven-
of the DUT. When the DUT is in the
tional DVCC cannot measure a voltage less than −1.7 on state, v = v
dsV, while . As shown in Figure
ds_onthe improved DVCC solves 6c, the
conventional DVCC
this problem (see cannot
Figure 6d).measure a voltage
Table 3 selects three less than −1.7 V,points,
measurement whilewhich
the improved
are locatedDVCC
solves this problem
at the moments when(see the Figure 6d). Table
first, second, 3 selects
and third threepeaks
negative measurement points, which
of the drain–source volt- are
located
age of the at DUT
the moments
occur, to when
compare thethefirst,
vds second, and third
(actual value) and thenegative
outputpeaks
voltageof vthe drain–
out. As

source
shown voltage
in Tableof3, the DUTthe
during occur, to compare
on-oscillation state, vds max
the the (actual value)
voltage and the output
measurement voltage
relative
verror
out . As shown
of the in Table 3,
conventional during
DVCC canthe on-oscillation
reach up to 78.8%, state,
whilethe max
the voltage
error value measurement
of the im-
proved DVCC
relative is the
error of reduced to less than
conventional 17.6%.
DVCC canThe comparison
reach resultswhile
up to 78.8%, of vdsthe
(actual
errorvalue)
value of
andimproved
the vout duringDVCC
the on-steady
is reducedstatetoare
lessshown in Table
than 17.6%. The4, comparison
which showsresults
that theofrelative
vds (actual
errors of
value) thevout
and on-steady
duringstate voltage measured
the on-steady state arebyshownthe conventional
in Table 4, DVCC
which andshowsthe that
im- the
proved DVCC are both within 1%. Furthermore, the conduction loss
relative errors of the on-steady state voltage measured by the conventional DVCC and the measurement errors
of the conventional
improved DVCC areDVCC and the1%.
both within improved DVCC,the
Furthermore, as conduction
shown in Table loss 5, are 6.42% and
measurement errors
of the conventional DVCC and the improved DVCC, as shown in Table 5, are 6.42% and
Sensors 2021, 21, 4285 13 of 19

0.78%, respectively, which proves the high accuracy of the conduction loss measurement of
the improved circuit.

Table 3. Comparison of vds and vout during the on-oscillation state.

Time Circuit vds /V vout /V Relative Error

Conventional −6.9 −1.7 75.4%
T1
Improved −14.3 −15.3 7.0%
Conventional −8.0 −1.7 78.8%
T2
Improved −10.3 −8.5 17.5%
Conventional −5.6 −1.7 77.0%
T3
Improved −7.4 −6.1 17.6%

Table 4. Comparison of vds and vout during the on-steady state.

Time Circuit vds /V vout /V Relative Error

Conventional 1.710399 1.717680 0.43%
T4
Improved 1.715286 1.724388 0.53%
Conventional 1.753108 1.752805 0.02%
T5
Improved 1.752987 1.752228 0.04%
Conventional 1.800825 1.800813 0.0007%
T6
Improved 1.800945 1.800930 0.0009%
Sensors 2021, 21, x FOR PEER REVIEW 13 of 19

Table 5. Comparison of conduction loss measurement.

Table 5. Comparison of conduction loss measurement.
Circuit Measure Directly/µJ Measure by DVCC/µJ Relative Error
Circuit
Conventional Measure Directly/μJ
35.733 Measure by38.027
DVCC/μJ Relative Error
6.42%
Conventional
Improved 35.733
37.010 38.027
36.721 6.42%
0.78%
Improved 37.010 36.721 0.78%
To more powerfully illustrate the reduction of conduction loss and on-state voltage
To more error,
measurement powerfully illustrate
simulations the reduction
under differentof conduction
voltages loss and on-stateDuring
are supplemented. voltagethe
measurement error, simulations under different voltages are supplemented. During
test, the V DC is set to 400 V and 600 V, respectively, and the measurement results are shown the
test, the VDC is set to 400 V and 600 V, respectively, and the measurement results are shown
in Figure 7.
in Figure 7.

40 40
vds vout Conventional DVCC vds vout Conventional DVCC
20 20
vds(V)
vds(V)

T1 T2 T3 T1 T2 T3
0 0
vds vout relative error vds vout relative error
T1 −6.55 −1.7 73.59% T1 −5.3 −1.74 67.42%
-20 -20
T2 −7.56 −1.6 78.31% T2 −7.2 −1.63 77.33%
T3 −4.97 −1.6 68.21% T3 −4.6 −1.59 65.73%
-40 -40
11.55 11.60 time(μs) 11.65 11.70 11.60 time(μs) 11.65 11.70
40 40
vds vout Improved DVCC vds vout Improved DVCC
20 20
vds(V)

vds(V)

0 T1 T2 T3 0 T2 T3
T1
vds vout relative error vds vout relative error
T1 −11.87 −13.7 T1 −11.4 −13.9 21.84%
-20 15.16%
-20
T2 −9.81 −8.02 18.25% T2 −9.77 −8.75 10.44%
T3 −6.31 −5.11 19.02% T3 −6.33 −5.65 10.74%
-40 -40
11.55 11.60 11.65 11.70 11.60 11.65 11.70
time(μs) time(μs)

(a) (b)

Figure
Figure 7. and
7. vds vds and
voutvout waveformcomparison
waveform comparisonduring
duringthe
the on-oscillation
on-oscillation state.
state. (a)
(a)VVDCDC
= 400 V; V;
= 400 (b)(b)
VDCV=DC
600=V.
600 V.

The relative error between vds (actual value) and vout during the on-oscillation state is
shown in Figure 7. Compared with the conventional DVCC, the measurement relative
error of the improved DVCC is significantly reduced. When VDC is 400 V and 600 V, the
maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%, re-
spectively. Furthermore, by comparing the conduction loss value measured by the con-
Sensors 2021, 21, 4285 14 of 19

The relative error between vds (actual value) and vout during the on-oscillation state
is shown in Figure 7. Compared with the conventional DVCC, the measurement relative
error of the improved DVCC is significantly reduced. When V DC is 400 V and 600 V,
the maximum relative errors are reduced from 78.31% and 77.33% to 19.02% and 21.84%,
respectively. Furthermore, by comparing the conduction loss value measured by the
conventional DVCC and the improved DVCC, it can be known that when the V DC is
400 V and 600 V, the relative errors are reduced from 6.60% and 6.85% to 1.07% and 1.65%,
respectively, which is shown in Table 6.

Table 6. Comparison of conduction loss measurement under different voltages.

Voltage Circuit Measure Directly/µJ Measure by DVCC/µJ Relative Error

Conventional 22.40 23.87 6.60%
400 V
Improved 23.32 23.07 1.07%
Conventional 52.92 56.55 6.85%
600 V
Improved 54.52 53.62 1.65%

4.1.2. Qualitative Experimental Verification

Sensors 2021, 21, x FOR PEER REVIEW 14 of 19
The comparative experiment of the on-oscillation state voltage measurement is carried
out in this section. Under the same working condition, the conventional DVCC and
improved DVCC are used to measure the on-state voltage of the DUT, respectively. The
improved
voltage DVCCovershoot
negative are used to measureby
measured thethe
on-state voltageis of
two circuits the DUT,and
compared, respectively.
the resultThe
is
voltage
shown innegative
Figure 8.overshoot measured by the two circuits is compared, and the result is
shown in Figure 8.

20 improved DVCC conventional DVCC

VDC=500V
10
vout(V)

-10
−9.3V
−20.6V
-20

-30
22.00 22.05 22.10 22.15 22.20
time(μs)

Figure 8. vout waveform comparison during the on-oscillation state.

Figure 8. vout waveform comparison during the on-oscillation state.

ItItcan
canbebeseen
seenfrom
fromFigure
Figure88that
thatcompared
comparedtotothetheimproved
improvedDVCC,
DVCC,the thedrain–source
drain–source
voltagenegative
voltage negativeovershoot
overshootmeasured
measuredby bythe
theconventional
conventionalDVCC
DVCCisissignificantly
significantlyreduced.
reduced.
Underthe
Under thetest
test voltage
voltage conditions of
of 500
500V,V,the
themeasurement
measurementresult
resultofofthe voltage
the negative
voltage nega-
overshoot is reduced by 11.3 V, which is consistent with the theoretical analysis
tive overshoot is reduced by 11.3 V, which is consistent with the theoretical analysis in in Section
2.2.1 and
Section theand
2.2.1 simulation verification
the simulation in Section
verification 4.2.1. 4.2.1.
in Section

4.2.
4.2.Working
WorkingSecurity
SecurityofofAuxiliary
AuxiliaryDevice
DeviceMOSFET
MOSFET
4.2.1.
4.2.1. Comparison of Work Security of MininConventional
Comparison of Work Security of M ConventionalDVCC
DVCCand
andImproved
ImprovedDVCC
DVCC
The
Theexperiments
experimentsare
arecarried
carriedout
oututilizing
utilizingthe
thetest
testplatform
platformshown
shownininFigure
Figure4,4,with
with
the
the primary circuit (DPTC) operating conditions unchanged. Due to the presenceofofthe
primary circuit (DPTC) operating conditions unchanged. Due to the presence the
gate-shunt
gate-shuntcapacitance,
capacitance,the
thegate–source
gate–sourcevoltage
voltagenegative
negativeovershoot
overshootofofMMmay
mayexceed
exceeditsits
tolerance limit. Therefore, the V DC is set to 400 V to ensure the safety of M. The current
tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The current
waveform flowing through V cc and the gate−source voltage waveform of M are shown in
waveform flowing through Vcc and the gate−source voltage waveform of M are shown in
Figure 9.
Figure 9.

1.2 20
Improved DVCC Improved DVCC
Conventional DVCC Conventional DVCC
0.8 0.71A
10
 4.2.1. Comparison of Work Security of M in Conventional DVCC and Improved DVC
The experiments are carried out utilizing the test platform shown in Figure 4, w
Sensors 2021, 21, x FOR PEER REVIEW 15 of 20
the primary circuit (DPTC) operating conditions unchanged. Due to the presence of
gate-shunt capacitance, the gate–source voltage negative overshoot of M may exceed
tolerance limit. Therefore, the VDC is set to 400V to ensure the safety of M. The curr
Sensors 2021, 21, 4285 15 of 19
tolerance limit. Therefore, the VDC through
waveform flowing is set toV400V
cc andto
theensure the safety
gate−source of waveform
voltage M. The current
of M are show
waveform flowing Figure 9. Vcc and the gate−source voltage waveform of M are shown in
through
Figure 9.
1.2 20
Improved DVCC Improved DVCC
1.2 20 Conventional DVCC
Conventional DVCC
0.8 Improved0.71A
DVCC Improved DVCC
10
Conventional DVCC Conventional DVCC
0.8 0.71A 0.43A
10

vgs_M(V)
0.4

i2(A)
0.43A 0

vgs_M(V)
0.4 −0.78V
0.0
i2(A)

0
−0.78V
-10
0.0
-0.4
-10 −14.12V
-0.4 -0.8 -20
15.9 16.0 16.1 16.2 16.3 16.4−14.12V15.9 16.0 16.1 16.2 16.3
time(μs) time(μs)
-0.8 -20
15.9 16.1 16.0
16.2 16.3 16.4 15.9 16.0 16.1 16.2 16.3
time(μs)
(a) time(μs) (b)
Figure 9. The current waveform flowing through Vcc and the gate−source voltage waveform of M. (a) Current waveform;
Figure the gate−source voltage waveform of M.
(a)9. The current waveform flowing through Vcc and(b)
(b) voltage waveform.
(a) Current waveform; (b) voltage waveform.
Figure 9. The current waveform flowing through Vcc and the gate−source voltage waveform of M. (a) Current waveform;
(b) voltage waveform. The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V
The improved DVCC reduces the absolute value of V gs_M(max) from 14.12 to 0.78 V but
increases the max current flowing through Vcc from 0.43 to 0.71 A. As seen, the increas
increases the max current flowing through V cc from 0.43 to 0.71 A. As seen, the increase
The improved DVCC reduces the absolute value of Vgs_M(max) from 14.12 to 0.78 V but
in current can be ignored because it is still far less than the impulse tolerance of the DC
increases the maxHowever,
voltage supply. current flowing
according through
to theVdatasheet,
cc from 0.43 to 0.71 A. As seen, the increase in
the gate−source withstand voltage
current can be ignored because it is still far less
limit V gs_limit of M is only −10 V. Therefore, the reduction than the impulse
of Vtolerance of the DC volt-
gs_M(max) from −14.12 to
age
−0.78 supply. However,
V makes according
M out of to the datasheet,
unsafe conditions, which the gate−source
significantly withstand
improves voltage
the work limit
security
Vofgs_limit
M. of M is only −10 V. Therefore, the reduction of Vgs_M(max) from −14.12 to −0.78 V

makes M out of unsafe conditions, which significantly improves the work security of M.
4.2.2. Work Security of M and V cc at Higher Voltages
4.2.2. ToWork Security
study of M andsafety
the working Vcc at ofHigher
V and Voltages
M in the improved DVCC under higher
cc
To study
voltages (500 the working
V, 600 V, 700safety
V, 800of V),
Vcc and M inexperiments
related the improved areDVCC
carriedunder
out. higher volt-
The circuit
ages (500 V, 600 V, 700 V, 800 V), related experiments are carried out. The
components are selected based on the selection theory proposed in this article to ensure circuit compo-
nents are selected
the safety based on the selection
of the experiments. Since thetheory
targetproposed
maximum in experimental
this article to ensure
voltagetheis safety
800 V,
of theisexperiments.
V D3 set to 7.5 V, VSince thetotarget
cc is set 7 V, Rmaximum to 50 Ω, andvoltage
experimental
2 is selected is 800 V,toV5D3Ωisfor
R3 is selected setthe
to
7.5 V, Vcc is set
experiment. Theto results
7 V, R2are
is selected
shown in toFigure
50 Ω, and
10. R3 is selected to 5 Ω for the experiment.
The results are shown in Figure 10.
1.2 15
500V 600V 700V 800V 500V 600V 700V 800V
VDC(V) i2(A)
0.8 10
500 
600 

vgs_M(V)

700
0.4 5
i2(A)

800 

0.0 0 VDC(V) EI1(V)

500 −1.46
600 −1.88
-0.4 -5 700 −2.49
800 −3.57
16.0 16.1 16.2 16.3 16.4 16.00 16.05 16.10 16.15 16.20
time(μs) time(μs)
(a) (b)
Figure
Figure 10.
10. The
Thecurrent
current waveform
waveform flowing
flowing through
through V
Vccccand
andthe
thegate−source
gate−sourcevoltage
voltagewaveform
waveformofofMMunder
underhigher
highervoltages.
voltages.
(a) Current waveform; (b) voltage waveform.
(a) Current waveform; (b) voltage waveform.

As shown in Figure 10, at higher voltages, the gate–source voltage negative overshoot
of M (EI1 ) is always within the maximum rating of the gate–source voltage of M. In addition,
Sensors 2021, 21, 4285 16 of 19

at the moment of turning off, the maximum current flowing through the DC source (V cc ) is
about 0.8 A, which is much smaller than the impulse current tolerance of the DC source.
Therefore, the improved circuit proposed in this article can still work effectively and safely
under high-voltage conditions.

4.3. Selection Method of Vcc and VD3

According to the working principle of the double pulse circuit and the device param-
eters of the DUT, when the off-state voltage of the DUT is 800 V, the maximum on-state
voltage V on_max can reach 3.2 V. Based on the selection mechanism and detailed analyses
in Section 3, set V cc to 7 V and V D3 to 7.5 V for the experiment. The results are depicted
Sensors 2021, 21, x FOR PEER REVIEW 16 of in
19
Figure 11.

15
500V 600V 700V 800V
10
vgs_M(V)

5
0 DUT is in the off−state DUT is in the
vgs_M=EI3 on−state
-5
vgs_M=EI2
-10
0 10 time(μs) 20 30
5 8
4 7
Vth_M
6
vgs_M(V)

vgs_M(V)

3
2 5
4
1 Vth_M
3
0
16 18 20 22 22 24 26
time(μs) time(μs)

Figure11.
11. The
The gate-source
gate-sourcevoltage
voltagewaveform
waveformofofM
Munder
underdifferent
differentvoltages
voltages(V(Vcc== 77 V,
V,VVD3 == 7.5 V).
Figure cc D3 7.5 V).

As shown
As shown in in Figure
Figure 11,11, under
under different
different voltages,
voltages, whenwhen the the DUT
DUT is
is in
inthe
theon
onstate,
state,itit
always meets EI > V , ensuring that M is
always meets EI2 > V th_M , ensuring that M is normally
2 th_M normally turned on. When the DUT is
the DUT is in inthe
the
off state, it satisfies EI < V , so that
off state, it satisfies EI3 < V th_M , so that M
3 th_M M is also in the off state. The experimental results
off state. The experimental results
provethe
prove therationality
rationalityof ofthe
theselection
selectionmethod
methodof ofVVcccc and VD3D3. .

4.4.
4.4. Selection
Selection Method
Method of of RR22 and R3
According
According to to Equations
Equations(28) (28)and
and(31), 1.52 Ω
(31),RR33>> 1.52 andRR22 << 55
Ωand 55 ΩΩ while
whilemeeting
meetingSSCSSC
and MEC. Using the controlled variable method,
and MEC. Using the controlled variable method, when cc when V , V R
D3, and R33 are determined,set
Vcc, VD3 , and are determined, set
to 55 Ω,
RR22 to 10 Ω,
Ω, 10 20 Ω,
Ω, 20 Ω, and
and 30 Ω for
30 Ω for the
the experiments.
experiments. Figure
Figure 12a
12a demonstrates
demonstrates the the measured
measured
EI
EI11 in
in the
the case
case of differentRR22.. Moreover,
of different Moreover,whenwhenRR22 is is determined,
determined,set setthe resistanceofofRR33to
theresistance to
55 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI
Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI1 with R3 is shown in
1 with R 3 is shown in
Figure
Figure 12b.
12b.
 4.4. Selection Method of R2 and R3
According to Equations (28) and (31), R3 > 1.52 Ω and R2 < 55 Ω while meeting SSC
and MEC. Using the controlled variable method, when Vcc, VD3, and R3 are determined, set
R2 to 5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. Figure 12a demonstrates the measured
Sensors 2021, 21, 4285 EI1 in the case of different R2. Moreover, when R2 is determined, set the resistance of17Rof3 to
19
5 Ω, 10 Ω, 20 Ω, and 30 Ω for the experiments. The variation of EI1 with R3 is shown in
Figure 12b.

(a) (b)
Sensors 2021, 21, x FOR PEER REVIEW
Figure12.
12. The
The variation
variationof
ofEI
EI1 with
with R
R2 and R3. (a) With R2; (b) with R3. 17 of 19
Figure 1 2 and R3 . (a) With R2 ; (b) with R3 .

As described in Figure 12, EI1 decreases with the increase in R2 , and it increases
with the describedininRFigure
As increase 3 . The12,
experimental
EI1 decreasesresults effectively
with the verify
increase in theitcorrectness
R2, and of the
increases with
theoretical
the increaseanalysis indicated
in R3. The in Section
experimental 3. When
results effectively verifyRthe
choosing 2 , the resistance
correctness should
of the be as
theo-
retical
large asanalysis
possibleindicated in Section
while meeting 3. In
SSC. When choosing
contrast, when R2,choosing
the resistance should
R3 , the be as large
resistance should
beasas
possible while
small as meeting
possible SSC.
while In contrast,MEC.
completing when choosing R3, the resistance should be as
small as possible while completing MEC.
4.5. Error Analysis
4.5. The
Errorsize
Analysis
of the error in on-state voltage and conduction loss measurement, using the
The size
improved of theiserror
DVCC, in on-state
further voltage
analyzed and conduction
to highlight loss measurement,
the accuracy over differentusing the
working
improved DVCC,
conditions. Based isonfurther analyzed
the circuit shownto highlight
in Figure the accuracy
5, the on-stateover different
voltage working
of the DUT is
conditions.byBased
measured on the circuit
the improved DVCC shown
underin Figure 5, the
the V DC on-state
of 300 V, 400voltage
V, 500ofV,the
600DUT is V,
V, 700
measured
and by the improved
800 V. Subsequently, DVCC under
utilizing the VDC ofon-state
the measured 300 V, 400 V, 500 the
voltage, V, 600 V, 700 V, and
conduction loss is
800 V. Subsequently,
calculated. Furthermore,utilizing the measuredresults
the measurement on-stateofvoltage,
improvedthe conduction loss is calcu-
DVCC are compared with
lated. Furthermore, the measurement results of improved DVCC
the actual value to get the relative error, which is shown in Figure 13. are compared with the
actual value to get the relative error, which is shown in Figure 13.
30 3.5
Relative error of the conduction loss Relative error of the first negative peak Maximun relative error of the
2.0 on-steady voltage measurement
measurement measurement in the on-oscillation state
Relative error(%)

2.8
Relative error(%)

25
Relative error(%)

<2.75%
1.5 <25% 2.1
<1.7%
20
1.4
1.0
15
0.7
0.5 10
300 400 500 600 700 800 300 400 500 600 700 800 300 400 500 600 700 800
VDC(V) VDC(V) VDC(V)

(a) (b) (c)

Figure 13. The measurement relative error of improved DVCC. (a) Conduction loss; (b) on-oscillation state voltage; (c) on-
Figure 13. The measurement relative error of improved DVCC. (a) Conduction loss; (b) on-oscillation state voltage;
steady state voltage.
(c) on-steady state voltage.
It can be seen from Figure 13 that when using the improved DVCC to measure the
conduction loss of the DUT, the relative error between the measurement result and the
actual value remains below 1.7%. In addition, at the moment of turning on, the measure-
ment relative error of the first negative peak is kept within 25%. Moreover, in the on-
steady state, the maximum relative error of the on-steady state voltage measurement is
within 2.75%. The above data effectively prove the high measurement accuracy of the im-
proved DVCC.
Sensors 2021, 21, 4285 18 of 19

It can be seen from Figure 13 that when using the improved DVCC to measure
the conduction loss of the DUT, the relative error between the measurement result and
the actual value remains below 1.7%. In addition, at the moment of turning on, the
measurement relative error of the first negative peak is kept within 25%. Moreover, in the
on-steady state, the maximum relative error of the on-steady state voltage measurement
is within 2.75%. The above data effectively prove the high measurement accuracy of the
improved DVCC.

5. Conclusions
An improved DVCC topology for measuring the conduction loss of power semicon-
ductor devices is proposed and fully characterized in this article. The proposed DVCC,
in comparison with the existing designs (conventional DVCC) through simulation and
experimentation, shows better accuracy and higher security. During the on-oscillation state,
the maximum relative error of the on-state voltage measurement decreased from 78.8% to
17.6%, and the on-state voltage measurement accuracy is greatly improved. Furthermore,
the relative error of the total conduction loss measurement of the two on-state stages is
reduced from 6.42% to 0.78%, which is one of the critical contributions of the proposed
approach. Another key advantage of the improved DVCC is that it improves the working
security of M, which is embodied in the reduction of the gate−source voltage negative
overshoot of the auxiliary device MOSFET from −14.12 to 0.78 V. In addition, the influence
of component parameters on the circuit performance of the improved DVCC is discussed,
and three electrical quantities are extracted as the judgment indicators for the component
selection, including the gate−source voltage negative overshoot (V gs_M(max) ) of M, the
gate−source voltage vgs_M(on) of M when the DUT is in the on state, and the gate−source
voltage vgs_M(off) of M when the DUT is in the off state. Finally, the component selection
criteria are given and validated by experimental results. First, the switching speed and
blocking voltage level of M should be consistent with or better than the DUT. Second, in the
case of meeting VCEW, the breakdown voltage of the Zener diode (D3 ) should be selected
to be a small value. Third, under the conditions of fulfilling MEC and SSC, the selection
guide for these two resistors is to increase R2 and decrease R3 as much as possible.

Author Contributions: Conceptualization, Q.Y., Z.Z., P.S., and B.Z.; methodology, Q.Y.; software, Q.Y.
and Z.Z.; validation, Q.Y., P.S., and Z.Z.; formal analysis, Q.Y. and Y.C.; investigation, Q.Y.; resources,
Q.Y.; data curation, B.Z.; writing—original draft preparation, Q.Y. and P.S.; writing—review and
editing, Q.Y.; visualization, Z.Z.; supervision, B.Z.; project administration, Q.Y., and P.S.; funding
acquisition, Z.Z. All authors have read and agreed to the published version of the manuscript.
Funding: This work was supported by State Grid science and technology projects (Electrical charac-
terization and screening method of press-pack IGBT chip (grant no. 5455GB190007).
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: The data used for the manuscript are available for researchers on request.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Zhao, Z.M.; Shi, B.C.; Zhu, Y.C. Control Technologies for Power Electronic Hybrid Systems in High-voltage High-power
Applications: A Review. High Volt. Eng. 2019, 45, 2017–2027.
2. Lagier, T.; Ladoux, P.; Dworakowski, P. Potential of silicon carbide MOSFETs in the DC/DC converters for future HVDC offshore
wind farms. High Volt. 2017, 2, 233–243. [CrossRef]
3. Gareau, J.; Hou, R.; Emadi, A. Review of Loss Distribution, Analysis, and Measurement Techniques for GaN HEMTs. IEEE Trans.
Power Electron. 2020, 35, 7405–7418. [CrossRef]
4. Fuentes, C.D.; Müller, M.; Bernet, S.; Kouro, S. SiC-MOSFET or Si-IGBT: Comparison of Design and Key Characteristics of a 690 V
Grid-Tied Industrial Two-Level Voltage Source Converter. Energies 2021, 14, 3054. [CrossRef]
5. Cai, Y.M.; Zhao, Z.B.; Liang, S.; Sun, P.; Yang, F. Influence of Parasitic Parameters of Commutation Path on Switching Characteris-
tics of Silicon Carbide MOSFET. High Volt. Eng. 2021, 47, 603–614.
Sensors 2021, 21, 4285 19 of 19

6. Sun, P.; Zhao, Z.; Cai, Y.; Ke, J.; Cui, X.; Ji, B. Analytical model for predicting the junction temperature of chips considering the
internal electrothermal coupling inside SiC metal-oxide-semiconductor field-effect transistor modules. IET Power Electron. 2020,
13, 436–444.
7. Chen, M.; Hu, A.; Tang, Y.; Wang, B. Modeling Analysis of IGBT Thermal Model High Voltage Engineering. High Volt. Eng. 2011,
37, 453–459.
8. Lei, W.J.; Liu, J.J.; Lv, G.T.; Lv, C.L.; Cao, R. Review of Reliability Comprehensive Analysis and Evaluation Methods for Key
Components and System of Large Capacity Power Electronic Equipment. High Volt. Eng. 2020, 46, 3353–3361.
9. Ladoux, P.; Blaquiere, J.M.; Alvarez, S.; Carroll, E.; Streit, P. Test bench for the characterisation of experimental low voltage IGCTs.
In Proceedings of the 35th Annual IEEE Power Electronics Specialists Conference (PESC 04), Aachen, Germany, 20–25 June 2004.
10. Anurag, A.; Acharya, S.; Bhattacharya, S. An Accurate Calorimetric Loss Measurement Method for SiC MOSFETs. IEEE J. Emerg.
Sel. Top. Power Electron. 2020, 8, 1644–1656. [CrossRef]
11. Li, H.; Li, X.; Zhang, Z.; Wang, J.; Liu, L.; Bala, S. A Simple Calorimetric Technique for High-Efficiency GaN Inverter Transistor
Loss Measurement. In Proceedings of the 5th IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA),
Albuquerque, NM, USA, 30 October–1 November 2017.
12. Johannesson, D.; Nawaz, M. Assessment of PSpice Model for Commercial SiC MOSFET Power Modules. In Proceedings of the
3rd IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Blacksburg, VA, USA, 2–4 November 2015.
13. Hsin-Ju, C.; Kusic, G.L.; Reed, G.F. Comparative PSCAD and Matlab/Simulink simulation models of power losses for SiC
MOSFET and Si IGBT devices. In Proceedings of the 2012 IEEE Power and Energy Conference at Illinois, Champaign, IL, USA,
24–25 February 2012.
14. Prasad, J.S.S.; Prasad, K.N.V.; Narayanan, G. Device Loss and Thermal Characteristics of High Power PWM Converters. In
Proceedings of the 8th IEEE India International Conference on Power Electronics (IICPE), Jaipur, India, 13–15 December 2018.
15. Lim, H.; Hwang, J.; Kwon, S.; Baek, H.; Uhm, J.; Lee, G. A Study on Real Time IGBT Junction Temperature Estimation Using the
NTC and Calculation of Power Losses in the Automotive Inverter System. Sensors 2021, 21, 2454. [CrossRef]
16. Ahmed, M.H.; Wang, M.; Hassan, M.A.S.; Ullah, I. Power Loss Model and Efficiency Analysis of Three-Phase Inverter Based on
SiC MOSFETs for PV Applications. IEEE Access 2019, 7, 75768–75781. [CrossRef]
17. Zhang, L.; Yuan, X.; Wu, X.; Shi, C.; Zhang, J.; Zhang, Y. Performance Evaluation of High-Power SiC MOSFET Modules in
Comparison to Si IGBT Modules. IEEE Trans. Power Electron. 2019, 34, 1181–1196. [CrossRef]
18. Gelagaev, R.; Jacqmaer, P.; Driesen, J. A Fast Voltage Clamp Circuit for the Accurate Measurement of the Dynamic ON-Resistance
of Power Transistors. IEEE Trans. Ind. Electron. 2015, 62, 1241–1250. [CrossRef]
19. Carsten, B. Clipping preamplifier provides accurate measurement of transistor conduction voltages. In Proceedings of the 31st
International Power Conversion Electronic Conference Exhibition, Long Beach, CA, USA, 9–15 September 1996.
20. Pokryvailo, A.; Carp, C. Accurate Measurement of on-State Losses of Power Semiconductors. In Proceedings of the Proceedings
of the 2008 IEEE International Power Modulators and High Voltage Conference, Las Vegas, NV, USA, 27–31 May 2008.
21. Ren, L.; Shen, Q.; Gong, C. A Voltage Clamp Circuit for the Real-Time Measurement of the On-State Voltage of Power Transistors.
In Proceedings of the 8th Annual IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, USA, 18–22
September 2016.
22. Ghimire, P.; de Vega, A.R.; Beczkowski, S.; Munk-Nielsen, S.; Rannested, B.; Thogersen, P.B. An online V-ce measurement and
temperature estimation method for high power IGBT module in normal PWM operation. In Proceedings of the International
Power Electronics Conference (IPEC-ECCE-ASIA), Hiroshima, Japan, 18–21 May 2014.
23. B˛eczkowski, S.; Ghimre, P.; de Vega, A.R.; Munk-Nielsen, S.; Rannestad, B.; Thøgersen, P. Online Vce measurement method for
wear-out monitoring of high power IGBT modules. In Proceedings of the 2013 15th European Conference on Power Electronics
and Applications (EPE), Lille, France, 2–6 September 2013.
24. Yu, B.; Wang, L.; Ahmed, D. Drain-Source Voltage Clamp Circuit for Online Accurate ON-State Resistance Measurement of SiC
MOSFETs in DC Solid-State Power Controller. IEEE J. Emerg. Sel. Top. Power Electron. 2020, 8, 331–342. [CrossRef]
25. Guacci, M.; Bortis, D.; Kolar, J.W. On-state voltage measurement of fast switching power semiconductors. CPSS Trans. Power
Electron. Appl. 2018, 3, 163–176. [CrossRef]
26. Li, R.; Wu, X.; Yang, S.; Sheng, K. Dynamic on-State Resistance Test and Evaluation of GaN Power Devices Under Hard- and
Soft-Switching Conditions by Double and Multiple Pulses. IEEE Trans. Power Electron. 2019, 34, 1044–1053. [CrossRef]
27. Lu, B.; Palacios, T.; Risbud, D.; Bahl, S.; Anderson, D.I. Extraction of Dynamic On-Resistance in GaN Transistors: Under Soft- and
Hard-Switching Conditions. In Proceedings of the 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS),
Waikoloa, HI, USA, 16–19 October 2011.
28. Wang, J.; Chung, H.S.-H.; Li, R.T.-H. Characterization and Experimental Assessment of the Effects of Parasitic Elements on the
MOSFET Switching Performance. IEEE Trans. Power Electron. 2013, 28, 573–590. [CrossRef]
29. Ke, J.J.; Zhao, Z.B.; XIe, Z.K.; Xu, P.; Cui, X. Analytical Switching Transient Model for Silicon Carbide MOSFET under the Influence
of Parasitic Parameters. Trans. China Electrotech. Soc. 2018, 33, 1762–1774.
30. Gelagaev, R.; Jacqmaer, P.; Everts, J.; Driesen, J. A Novel Voltage Clamp Circuit for the Measurement of Transistor Dynamic
On-Resistance. In Proceedings of the 29th Annual IEEE International Instrumentation and Measurement Technology Conference
(I2MTC), Graz, Austria, 13–16 May 2012.