Industrial Electronics I: IE501 Semester 1, 2020-21

Industrial Electronics I
IE501
Lecture 9
Semester 1, 2020-21
Topics Covered
This presentation will cover:
• Latches
• Flip-flops
• Timers
Semester 1, 2020-21 IE501, Lecture 9 2

Reading For This Week
• Thomas Floyd, Digital Fundamentals : A Systems Approach, 9th Ed., USA: Prentice Hall.
– Read chapter 7 on latches, flip-flops & timers.
• Kuphaldt, Tony R. (2014). Lessons In Electric Circuits, Vol IV —Digital.

– Read Chapter 10 on Multivibrators.
– http://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_10.html
– This is a free online book available at the above link. Also available for download as a pdf
file.
– See also the associated website: http://www.allaboutcircuits.com/
• Neil Storey, Electronics, A Systems Approach, 5th Ed., Pearson

– Read Chapter 25 on sequential logic.
• Roger Tokheim, Schaum’s Outline of Theory & Problems of Digital Principles, 3 rd Ed.,
McGraw-Hill.
– Read Chapter 9 on Flip-flops & other multivibrators.

Latches
A latch is a temporary storage device that has two stable states
(bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds to
active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.
Latches – Active HIGH SR Latch

Latches – Active LOW SR Latch

Latches
Negative-OR equivalent of the NAND gate S-R latch

Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal is RESET
0
1
applied to the S input while the R Q
0 S
remains LOW.
0 R 1
0
To RESET the latch (Q = 0), a Q
momentary HIGH signal is applied Latch
to the R input while the S remains initially
LOW. SET
1
0
Q
0 S
Note that the outputs change according to
input levels. A latch is a level-triggered device.
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1

0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal is RESET
applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 1
0
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R

Latches
The three modes of
basic S-R operation:
(a) SET
(b) RESET
(c) no-change
Plus:
(d) invalid condition

Latches
Note: These latch & flip-flop truth tables are also known as
characteristic tables.

Latches
_ _
Logic symbols for the S-R and S-R latch.

Latches
Example_ _timing diagram
for the S-R latch.

Latches
_ _
Application: The S-R latch used to eliminate
switch contact bounce.

Latches
_ _
The 74HC279A quad S-R It features four internal latches with two
latch. having two S inputs. To SET any of the
latches, the S line is pulsed low. It is
available in several packages.

Gated S-R Latch
A gated latch is a variation on the basic latch.
The gated latch has
an additional input,
called enable (EN)
that must be HIGH
in order for the latch
to respond to the S
and R inputs.
Show the Q output with relation to the input signals.
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Gated S-R Latch Made From NAND gates

Gated S-R Latch Made From AND and NOR gates

Gated D Latch
The D latch is a variation of the S-R latch but combines the
S and R inputs into a single D input as shown:
A simple rule for the D latch is:

Q follows D when the EN is active.

Gated D Latch
D Q
EN
Determine the Q output for the
Q
D latch, given the inputs shown.
Notice that the Enable is not active during these times, so

the output is latched. When the Enable is active (in this
case, a HIGH level), the outputs change according to input
levels. A gated latch is also a level-triggered device.
Gated D Latch

D Latch

The 74HC75 quad D latch.
The truth table for the D latch summarizes
its operation. If EN is LOW, then there is
no change in the output and it is latched.

Flip-flops
A flip-flop differs from a latch in the manner in which it
changes states. A flip-flop is a clocked device, in which
only the clock edge determines when a new bit is
entered.
It is an edge-triggered device.
The active edge can be
positive or negative.
A flip-flop is also called a

Bistable multivibrator

Edge-Triggered Flip-flops
The output from an edge-

triggered flip-flop changes
on the positive-going or
negative-going edge of its
clock signal.
A bubble on the clock

input indicates that it is a
negative-edge triggered
flip-flop.

Edge-Triggered D Flip-flops
The data bit at the D-input is transferred to the component output
on the edge of the clock signal.
Once triggered, the output (Q) equals the last value at the D input
until a new value is triggered in.

The truth (or characteristic) table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its D input only on the
rising edge of the clock; otherwise it is latched. The truth table for a negative-
edge triggered D flip-flop is identical except for the direction of the arrow.

The timing diagram shows that Q
follows D, but ONLY on the positive
clock edge. Otherwise Q (and ) will not
change.

J-K Flip-flops
The values at the J and K inputs to a J-K flip-flop determine its output
state. The results of the four possible input combinations of J and K
are shown.

J-K Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In addition to the
clock input, it has two inputs, labeled J and K. When both J and K = 1,
the output changes states (toggles) on the active clock edge (in this
case, the positive-going or rising edge).

J-K Flip-flops
J Q
CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q
Notice that the outputs change on the positive-going or leading

edge of the clock.
Set Toggle Set Latch
CLK

J-K Flip-flops
The versatility of the J-K flip-flop allows it to be used to
reproduce other flip-flop functionality. This is why it is
sometimes referred to as a “universal” flip-flop.
Note: The S-R flip-flop behaves the same as the J-K flip-flop,
except that when both S and R = 1 it enters an invalid state,
exactly like the S-R latch.
Master/Slave Flip-flops
•• These
overcome race hazards by responding to the state of the
inputs shortly before the clock trigger.
• This master-slave J-K flip-flop responds internally to the state of
the inputs when the clock goes high, but only updates the
outputs (Q & ) on the falling clock edge.


•• This
is a master-slave D flip-flop implementation.
• Like the previous J-K flip-flop, this flip-flop responds internally
to the state of the inputs when the clock goes high, but only
updates the outputs (Q & ) on the falling clock edge.


Flip-flop Asynchronous Inputs
Synchronous (clocked) inputs are transferred on the triggering edge
of the clock. Most flip-flops have other inputs that are
asynchronous, meaning they operate independently of the clock.
Asynchronous flip-flop inputs are normally labeled preset (PRE) and clear
(CLR). These inputs are usually active LOW. A J-K flip flop with active LOW
preset and CLR is shown.
Note that the asynchronous inputs always override the synchronous inputs.

Flip-flop With Active Low Asynchronous
Inputs

Flip-flop Asynchronous PRE
Inputs Q
J
CLK
Determine the Q output for the J-K K Q

flip-flop, given the inputs shown.
CLR
Set Toggle Set Reset Toggle Latch

CLK
K Set
PRE Reset
CLR
Q
Flip-Flop Characteristics
Flip-Flop Propagation Delay
Propagation delay time is specified for the rising and falling
outputs. It is measured between the 50% level of the clock to the
50% level of the output transition.
Propagation delay (tPLH) is measured as shown in (a). Propagation delay

(tPHL) is measured as shown in (b).
Flip-flop Propagation Delay
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in
the output. Again it is measured from the 50% levels.

Flip-flop Set-up Time
Another time-related specification is flip-flop set-up time (ts).
This is the minimum time for an input to the D (or J-K) flip-flop
to be present before the triggering edge of the CLK signal for
reliable data entry into the flip-flop.

Flip-flop Hold Time
Another time-related specification is flip-flop hold time.
This is the minimum time over which the input to the D (or
J-K) flip-flop must remain stable after the arrival of the
triggering edge of the CLK input for reliable data entry into
the flip-flop.

Flip-flop Applications
Output
lines
Principal flip-flop applications are for Q0
temporary data storage, as frequency

dividers, and in counters (which are Q1
covered in detail in Floyd, Chapter 9).
Q2
Typically, for data storage
applications, a group of flip-flops are Parallel data
input lines
connected to parallel data lines and Q3
clocked together. Data is stored until Clock
the next clock pulse. This circuit is
Clear
called a shift register (covered in
Floyd, Chapter 8).
Flip-Flop Frequency Division
Flip-flops can be used as frequency dividers, as shown below.
One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and so on). A side
benefit of frequency division is that the output has an exact 50% duty cycle.
The D and J-K flip flops on the left are wired as “divide-by-2” circuits.
The J-K flip-flops on the right are cascaded to form a “divide-by-4” circuit.
Flip-Flop Counters
Flip-flops can be
used to count the
number of clock
signals they receive
as shown here.
Each CLK input triggers
the flip-flops, which are
wired to toggle whenever
triggered.
The QA and QB outputs
indicate the number of
CLK inputs received.

One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to its
unstable state for a predetermined length of time, then
returns to its stable state.
+V Basic logic symbol
of a one-shot
REXT CEXT
For most one-shots, the length of Q
CX
time in the unstable state (tW) is RX/CX
Trigger
determined by an external RC circuit.
Q
Trigger
Q
tW

Nonretriggerable One-Shots
A nonretriggerable one-shot does not respond to any
triggers that occur while in its unstable state, as shown here.

Retriggerable One-Shots
Retriggerable one-shots respond to any trigger, even if it
occurs while the component is in its unstable state. If it
occurs during the unstable state, the state is extended by an
amount equal to its normal output pulse width.

Logic symbol for the 74LS122 retriggerable one-
shot.

A One-Shot Sequential Timer
One-shots can be wired (as shown) to form a sequential
timer; a circuit that can set up a sequence of actions, such
as lighting a group of lights in a particular order.

A One Shot Power Failure Detection Circuit
An application for a retriggerable one-shot is a power failure
detection circuit.
• Triggers are derived from the ac power line frequency
o f = 50 Hz, ⸫ T = 20 ms
• These continue to retrigger the one shot if: the one shot pulse
width tw > T
• In the event of a power failure, the one-shot is not triggered and
an alarm can be initiated.
Missing trigger
Triggers
due to power
derived
failure
from ac
Q Retriggers Retriggers Power failure indication

tW
tW
tW
555 Timer One-Shot
The 555 timer can be configured in various ways, including as
a one-shot. A basic one-shot is shown. The pulse width is
approximately tW = 1.1R1C1.
+VCC
R1
RESET VCC
DISCH
THRESH OUT
The trigger is a
negative-going tW = 1.1R1C1
TRIG CONT
pulse. GND
C1

555 Timer Astable Multivibrator
An astable multivibrator (also called a free-running
multivibrator) is a circuit that produces a steady stream of
output pulses as long as power is applied.
In this circuit C1 charges

through R1 and R2 and
discharges through only
R2. The output frequency
is given by:

Frequency of oscillation as a function of C1 and R1 + 2R2. The sloped lines are values
of R1 + 2R2.
+VCC
R1
RESET VCC
DISCH
R2 THRESH OUT
TRIG CONT
C1 GND

Example: Calculate the frequency of oscillation given the circuit below.

Key Terms
Latch A bistable digital circuit used for storing a bit.
Bistable Having two stable states. Latches and flip-

flops are bistable multivibrators.
Clock A triggering input of a flip-flop.
D flip-flop A type of bistable multivibrator in which the

output assumes the state of the D input on the
triggering edge of a clock pulse.
J-K flip-flop A type of flip-flop that can operate in the SET,
RESET, no-change, and toggle modes.
Key Terms
Propagation The interval of time required after an input
delay time signal has been applied for the resulting
output signal to change.
Set-up time The time interval required for the input levels
to be on a digital circuit.
Hold time The time interval required for the input levels
to remain steady to a flip-flop after the
triggering edge in order to reliably activate the
device.
Timer A circuit that can be used as a one-shot or as
an oscillator.
Key Terms
Monostable Having one stable state (& one metastable

state). One-shots are monostable multivibrators.
Astable Having no stable states (just two metastable
states). An astable multivibrator oscillates
between the two metastable states, producing
a continuous stream of pulses.

Questions, Comments, Remarks

Materials
Content adapted from presentation materials
for:
• Thomas Floyd, Digital Fundamentals: A Systems Approach, 9th
Ed., USA: Prentice Hall. © 2013 Pearson Higher Education,
Inc.
• Storey, N. (2013). Electronics a Systems Approach 5th Edition.

England: Pearson Education Ltd., 2013

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Industrial Electronics I

Semester 1, 2020-21 IE501, Lecture 9 2

• Kuphaldt, Tony R. (2014). Lessons In Electric Circuits, Vol IV —Digital.

• Neil Storey, Electronics, A Systems Approach, 5th Ed., Pearson

Semester 1, 2020-21 IE501, Lecture 9 3

Semester 1, 2020-21 IE501, Lecture 9 5

Semester 1, 2020-21 IE501, Lecture 9 6

Semester 1, 2020-21 IE501, Lecture 9 9

Assume the latch is initially RESET 1 S 1

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Semester 1, 2020-21 IE501, Lecture 9 16

Semester 1, 2020-21 IE501, Lecture 9 17

Semester 1, 2020-21 IE501, Lecture 9 19

Semester 1, 2020-21 IE501, Lecture 9 20

A simple rule for the D latch is:

Semester 1, 2020-21 IE501, Lecture 9 21

Notice that the Enable is not active during these times, so

Semester 1, 2020-21 IE501, Lecture 9 23

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Semester 1, 2020-21 IE501, Lecture 9 25

A flip-flop is also called a

Semester 1, 2020-21 IE501, Lecture 9 26

The output from an edge-

A bubble on the clock

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Notice that the outputs change on the positive-going or leading

Set Toggle Set Latch

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Semester 1, 2020-21 IE501, Lecture 9 40

Determine the Q output for the J-K K Q

Set Toggle Set Reset Toggle Latch

Propagation delay (tPLH) is measured as shown in (a). Propagation delay

Semester 1, 2020-21 IE501, Lecture 9 43

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Semester 1, 2020-21 IE501, Lecture 9 45

temporary data storage, as frequency

Semester 1, 2020-21 IE501, Lecture 9 48

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Q Retriggers Retriggers Power failure indication

Semester 1, 2020-21 IE501, Lecture 9 55

In this circuit C1 charges

Semester 1, 2020-21 IE501, Lecture 9 56

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Semester 1, 2020-21 IE501, Lecture 9 58

Bistable Having two stable states. Latches and flip-