Chapter Six

Sequential logic circuit

design
 Introduction
▪ Sequential circuit is made up of combinational circuit and
memory element to store the binary information
▪ The most important memory element is flip-flops, which are
made up of assembly of logic gates that permits information
to be stored.
▪ Flip-flop stores one bits and also known as latches
▪ However, flip-flops are associated with the device that
change a state only on a clock edge or pulse, where as
latches change a state at any time.
▪ But both are bistable (has two state 0 or 1) and both are used
to store information
 1. Latches
▪ A latch is a temporary storage device that has two stable states (bistable).
▪ The output of latch are always complement to each other
▪ There are three types of latches:
✓ S-R latch, Gated latch and Gated-D latch
1. The S-R (Set-Reset) latch : is the most basic type and can be
constructed from NOR gates or NAND gates.
✓ With NOR gates, the latch responds to active-HIGH inputs; with
NAND gates, it responds to active-LOW inputs.
R S
Q Q

Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch
 1. Latches

▪ The NAND active-LOW S-R latch is in a stable (latched)

condition when both inputs are HIGH.
✓ Assume the latch is initially
RESET (Q = 0) and the inputs
1 S 1
0
are at their inactive level (1). Q
✓ To SET the latch (Q = 1), a Latch
momentary LOW signal is initially
RESET
applied to the S input while the 1
0
Q
R remains HIGH. 1 R

✓ To RESET the latch a 1 S 1

0
Q
momentary LOW is applied to
Latch
the R input while S is HIGH. initially
✓ Never apply an active set 1 SET
0
Q
and reset at the same time 1R
(invalid).
 1. Latches

▪ The NOR active-HIGH S-R latch is in a stable (latched)

condition when both inputs are LOW.
✓ Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (0). 0 R 1
0
Q
✓ To SET the latch (Q = 1), a Latch
momentary HIGH signal is applied initially
to the S input while the R remains RESET
10
LOW. Q
0 S
✓ To RESET the latch (Q = 0), a
momentary HIGH signal is 0 R 1
0
Q
applied to the R input while the Latch
S remains LOW. initially
SET
✓ Never apply an active set 1
0
Q
and reset at the same time 0 S
(invalid).
 1. Latches

2. A Gated S-R latch: is a variation on the basic latch.

• The gated latch has an additional
input, called enable (EN) that
S
must be HIGH in order for the Q
latch to respond to the S and R
inputs. EN

Show the Q output with Q

relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
 1. Latches

3. The Gated-D latch : is an variation of the S-R latch but

combines the S and R inputs into a single D input as shown:

D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.
 1. Latches

▪ The truth table for the D latch summarizes its operation.

▪ If EN is LOW, then there is no change in the output and it is
latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
 1. Latches

Determine the Q output for the D Q

D latch, given the inputs shown.

EN

EN

Notice that the Enable is not active during these times, so

the output is latched.
 2. Flip-flops
▪ A flip-flop differs from a latch in the manner it changes states.
▪ A flip-flop is a clocked device, in which only the clock edge
determines when a new bit is entered.
▪ The active edge can be positive or negative.

D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
 2. Flip-flops
▪ The truth table for a positive-edge triggered D flip-flop shows an
up arrow to remind you that it is sensitive to its D input only on
the rising edge of the clock; otherwise it is latched.
▪ The truth table for a negative-edge triggered D flip-flop is
identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

 2. Flip-flops

▪ The J-K flip-flop is more versatile than the D flip flop.

▪ In addition to the clock input, it has two inputs, labeled J and K.
▪ When both J and K = 1, the output changes states (toggles) on
the active clock edge (in this case, the rising edge).

Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle
 2. Flip-flops

Determine the Q output for the J-K J Q

flip-flop, given the inputs shown.
CLK

K Q

Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

Q
 Counting in Binary

▪ A counter can form the same pattern of 0’s and 1’s with logic
levels.
▪ The first stage in the counter represents the least significant
bit – notice that these waveforms follow the same pattern as
counting in binary.

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0
 Three bit Asynchronous Counter

▪ In an asynchronous counter, the clock is applied only to the first

stage.
▪ Subsequent stages derive the clock from the previous stage.
▪ The three-bit asynchronous counter shown is typical. It uses J-K
flip-flops in the toggle mode.

HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

Waveforms are on the following slide…

 Three bit Asynchronous Counter

▪ Notice that the Q0 output is triggered on the leading edge of the

clock signal.
▪ The following stage is triggered from Q0.
▪ The leading edge of Q0 is equivalent to the trailing edge of Q0.
▪ The resulting sequence is that of an 3-bit binary up counter.
1 2 3 4 5 6 7 8
CLK

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0
 Propagation Delay
▪ Asynchronous counters are sometimes called ripple counters,
because the stages do not all change together.
▪ For certain applications requiring high clock rates, this is a
major disadvantage.

CLK 1 2 3 4
Notice how delays
are cumulative as Q0
each stage in a Q1
counter is clocked
later than the Q2
previous stage.

Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays.

 Asynchronous Decade Counter

▪ This counter uses partial decoding to recycle the count sequence

to zero after the 1001 state.
▪ The flip-flops are trailing-edge triggered, so clocks are derived
from the Q outputs.
▪ Other truncated sequences can be obtained using a similar
technique.
CLR
HIGH
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

Waveforms are on the following slide…

 Asynchronous Decade Counter

When Q1 and Q3 are HIGH together, the counter is cleared by

a “glitch” on the CLR line.

CLK 1 2 3 4 5 6 7 8 9 10

Q0

Q1 Glitch
Glitch

Q2

Q3

CLR
Glitch
Glitch
 The 74LS93A Asynchronous Counter
▪ The 74LS93A has one independent toggle J-K flip-flop driven by
CLK A and three toggle J-K flip-flops that form an asynchronous
counter driven by CLK B.
▪ The counter can be extended to form a 4-bit counter by
connecting Q0 to the CLK B input.
▪ Two inputs are provided that clear the count.
(1)
CLK B

J J1 J2 J3
0
(14)
CLK A C C C C

K0 K1 K2 K3

(2)
All J and K inputs RO (1)
(3)
are connected RO (2)
(12) (9) (8) (11)
internally HIGH
Q0 Q1 Q2 Q3
 Synchronous Counters
▪ In a synchronous counter all flip-flops are clocked together with
a common clock pulse.
▪ Synchronous counters overcome the disadvantage of accumulated
propagation delays, but generally they require more circuitry to
control states changes.

HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J J1 J
has the same count 0 2

C C C
sequence as the 3-bit
asynchronous counter K0 K1 K2

shown previously. CLK

The next slide shows how to analyze this counter by writing the logic
equations for each input. Notice the inputs to each flip-flop…
 Analysis of Synchronous Counters
▪ A tabular technique for analysis is illustrated for the counter
on the previous slide.
▪ Start by setting up the outputs as shown, then write the logic
equation for each input. This has been done for the counter.
1. Put the counter in an 2. Use the new inputs to 3. Set up the next
arbitrary state; then determine determine the next state: Q2 and group of inputs from
the inputs for this state. Q1 will latch and Q0 will toggle. the current output.

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0
4. Q2 will latch again but both Q1 and Q0 will toggle.

Continue like this, to complete the table.

The next slide shows the completed table…
 Analysis of Synchronous Counters

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1

1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1
0 0 0
At this points all states have been accounted
for and the counter is ready to recycle…
 A 4-bit Synchronous Binary Counter

Q1Q0
G1 Q2Q1Q0
G2
FF0 FF1 FF2 FF3

HIGH J0 Q0 J1 Q1 J2 Q2 J3 Q3

CLK C C C C

K0 Q0 K1 Q1 K2 Q2 K3 Q3

The 4-bit binary counter

has one more AND gate Q0
than the 3-bit counter just
described. The shaded Q1
areas show where the
AND gate outputs are Q2

HIGH causing the next

Q3
FF to toggle.
 BCD Decade Counter

▪ With some additional logic, a binary counter can be converted

to a BCD synchronous decade counter.
▪ After reaching the count 1001, the counter recycles to 0000.

This gate detects 1001, and causes FF3 to toggle on the next
clock pulse. FF0 toggles on every clock pulse. Thus, the count
starts over at 0000.
Q3
HIGH Q0
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK
 BCD Decade Counter

Waveforms for the decade counter:

CLK 1 2 3 4 5 6 7 8 9 10

Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

These same waveforms can be obtained with an asynchronous

counter in IC form – the 74LS90. It is available in a dual version –
the 74LS390, which can be cascaded. It is slower than synchronous
counters (max count frequency is 35 MHz), but is simpler.
 A 4-bit Synchronous Binary Counter

▪ The 74LS163 is a 4-bit IC synchronous counter with additional

features over a basic counter.
▪ It has parallel load, a CLR input, two chip enables, and a ripple count
output that signals when the count has reached the terminal count.

Data inputs
D0 D1 D2 D3

(3) (4) (5) (6)

CLR (1) CTR DIV 16

(9)
LOAD
(10) (15)
ENT TC = 15 RCO
(7)
ENP
(2)
CLK C

(14) (13) (12) (11)

Q0 Q1 Q2 Q3
Example waveforms
Data outputs
are on the next slide…
 A 4-bit Synchronous Binary Counter
CLR
LOAD
D0
D1
Data
inputs D2

D3

CLK
ENP
ENT

Q0
Q1
Data
outputs Q2
Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
Clear Preset
 Up/Down Synchronous Counters

▪ An up/down counter is capable of progressing in either

direction depending on a control input.

UP Q0.UP
HIGH
FF0 FF1 FF2
Q2
J J1 J2
0 Q0 Q1
UP/DOWN C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0.DOWN
CLK

Example waveforms from Multisim are on the next slide…

 Up/Down Synchronous Counters

D0 D1 D2 D3 Data inputs

(15) (1) (10) (9)

The 74HC190 is a high speed 74HC190
(4) (12)
CTEN MAX/MIN
CMOS synchronous up/down D/U
(5)
(11) CTR DIV 10
decade counter with parallel load LOAD (14) (13)
CLK C RCO
capability. It also has a active
(3) (2) (6) (7)
LOW ripple clock output (RCO)
and a MAX/MIN output when the Q0 Q1 Q2 Q3 Data outputs

terminal count is reached.

D0 D1 D2 D3 Data inputs

(15) (1) (10) (9)

The 74HC191 has the same 74HC191
(4) (12)
CTEN MAX/MIN
inputs and outputs but is a D/U
(5)
(11) CTR DIV 16
synchronous up/down binary LOAD (14) (13)
CLK C RCO
counter.
(3) (2) (6) (7)

Q0 Q1 Q2 Q3 Data outputs
 Synchronous Counter Design

▪ Most requirements for synchronous counters can be met with

available ICs.
▪ In cases where a special sequence is needed, you can apply a
step-by-step design process.
• The steps in design are described in detail in the text and lab manual. Start
with the desired sequence and draw a state diagram and next-state table.
The gray code sequence from the text is illustrated:
State diagram: Next state table:
000 Present State Next State
100 001 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
111 010 1 1 0 1 1 1
1 1 1 1 0 1
110 1 0 1 1 0 0
1 0 0 0 0 0
 Synchronous Counter Design

▪ The J-K transition table lists all combinations of present output

(QN) and next output (QN+1) on the left.
▪ The inputs that produce that transition are listed on the right.

Each time a flip-flop is clocked, the Output Flip-Flop

J and K inputs required for that Transitions Inputs
QN Q N+1 J K
transition are mapped onto a K-map.
Q0
0 0 0 X
Q2Q1 0 1 0 1 1 X
An example of 1 0 X 1
00 1 X Q2Q1 1 1 X 0
the J0 map is:
01 0 X

11 1 X Q2Q1 The logic for each input is read

10 0 X and the circuit is constructed.
J0 map The next slide shows the circuit
for the gray code counter…
 Synchronous Counter Design

FF0 FF1 FF2

Q2
J J1 J
0 Q0 Q1 2

C C C
Q0 Q1 Q2
K0 K1 K2

CLK

The circuit can be checked with Multisim before constructing it.

The next slide shows the Multisim result…
 Cascaded counters

▪ Cascading is a method of achieving higher-modulus counters.

▪ For synchronous IC counters, the next counter is enabled only
when the terminal count of the previous stage is reached.

HIGH
ƒin
Counter 1 Counter 2
16 fout ƒin
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin

a) What is the modulus of the cascaded DIV 16 counters?

b) If fin =100 kHz, what is fout?
a) Each counter divides the frequency by 16. Thus the
modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz
 Counter Decoding

▪ Decoding is the detection of a binary number and can be

done with an AND gate.

HIGH

Q2
J0 Q0 J1 Q1 J2 Q2

C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

What number is decoded by

this gate?
Decoded 4
Q2Q1Q0
 Partial Decoding

▪ The decade counter shown previously incorporates partial

decoding (looking at only the MSB and the LSB) to detect
1001.
▪ This was possible because this is the first occurrence of this
combination in the sequence.

Detects 1001 by looking only at two bits

HIGH
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK
 Resetting the Count with a Decoder

▪ The divide-by-60 counter in the text also uses partial decoding to

clear the tens count when a 6 was detected.

CLR CTR DIV 10 CLR CLR CTR DIV 6

RCO
HIGH CTEN TC = 9 CTEN

C C
CLK To next
Decode 6 counter

TC = 59
To ENABLE
Decode 59 of next CTR
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

units tens

The divide characteristic illustrated here is a good way to obtain a

lower frequency using a counter. For example, the 60 Hz power line
can be converted to 1 Hz.
 Counter Decoding

Show how to decode state 5 with an active LOW output.

HIGH

Q0 Q2
J0 Q0 J1 Q1 J2 Q2

C C C

Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

Notice that a NAND gate

was used to give the active
Decoded 5
LOW output.
Q2Q1Q0
 Logic Symbols

▪ Dependency notation allows the logical operation of a device

to be determined from its logic symbol.

Common
CTR DIV 16 control
(1) block
CLR (9)
5CT = 0
D0 D1 D2 D3 LOAD M1
(15)
M2 RCO
(3) (4) (5) (6) (10)
ENT G3
(7)
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) CTR DIV 16 (15)
ENT RCO (3) (14)
(7) D0 Q0
ENP 1, 5 D [1]
(2) (4) (13)
CLK C D1 [2] Q1
(5) (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 [8] Q3
Q0 Q1 Q2 Q3
 Basic Shift Register Operations

▪ A shift register is an arrangement of flip-flops with important

applications in storage and movement of data.
▪ Some basic data movements are illustrated here.

Data in

Data in Data out Data out Data in Data out

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
 Serial-in/Serial out Shift Register

▪ Shift registers are available in IC form or can be constructed from

discrete flip-flops as is shown here with a five-bit serial-in serial-
out register.
▪ Each clock pulse will move an input bit to the next flip-flop. For
example, a 1 is shown as it moves across.

FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output

C C C C C

CLK
CLK
 A Basic Application

▪ An application of shift registers is conversion of serial data to

parallel form.
▪ For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.

After 4 clock pulses, the data is available at the parallel output.

FF0 FF1 FF2

FF2 FF3
FF3
Serial 1
X
0 1
0 11
0 10 11
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
C
C C
C C
C C
C

CLK
CLK
 The 74HC164A Shift Register
▪ The 74HC164A is a CMOS 8-bit serial in/parallel out shift
register. VCC can be from +2.0 V to +6.0 V.

(9)
CLR
(8)
CLK
(1)
Serial A
R R R R R R R R
inputs B (2)
C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

One of the two serial data inputs may be used as an active HIGH
enable to gate the other input. If no enable is needed, the other serial
input can be connected to VCC. The 74HC164A has an active LOW
asynchronous clear. Data is entered on the leading-edge of the clock.
 Waveforms for the 74HC164A

▪ Sample waveforms CLR

for the 74HC164A Serial

A

are shown. Notice inputs B

that B acts as an CLK
active HIGH enable Q0
for the data on A as Q1
discussed.
Q2
▪ As with CMOS Q3
devices, unused Outputs
Q4
inputs should Q5
always be
Q6
connected to a
Q7
logic level; unused
outputs should be Clear Clear
left open.
 Parallel in/Serial out Shift Register

▪ Shift registers can be used to convert parallel data to serial form.

▪ A logic diagram for this type of register is shown:
D0 D1 D2 D3

SHIFT/LOAD

G1 G5 G2 G6 G3 G7 G4

Serial
D D D D
Q0 Q1 Q2 Q3 data out
C C C C

FF0 FF1 FF2 FF3

CLK
 The 74HC165 Shift Register

▪ The 74HC165 is a CMOS 8-bit parallel in/serial out shift

register.
▪ The logic symbol is shown:
D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD SRG 8 Q7
(10)
SER
(15)
CLK INH (2) (7)
CLK C Q7

The clock (CLK) and clock inhibit (CLK INH) lines are connected to a
common OR gate, so either of these inputs can be used as an active-
LOW clock enable with the other as the clock input. Data is loaded
asynchronously when SH/LD is LOW and moved through the register
synchronously when SH/LD is HIGH and a rising clock pulse occurs.