EE-307

DIGITAL SYSTEM DESIGN

Introduction
Course Description
Design Space Exploration
Digital Design Methodology

Lecture # 02 Slides taken from Dr. Rehan Hafiz

Today’s Lecture

 Introduction
 What are Digital Systems ?

 What shall you learn in this course ?

 Where you can apply the learned

knowledge?
 Will this course open any new job horizon

for you ?
Camera-1 Camera-2

I(x,y) I`(x,y)
T(x,y)
Overlapping
region

Panorama Generation

VISpro
 Stitching FIVE Views

Projection using THREE Overlapping Projectors

VISpro
A Multi View Imaging (MVI) Processing Platform:
FPGA based Real Time Panoramic Mosaic Generation

VISpro
What are Digital Systems ?
A digital system[1] is a data technology that uses
discrete (discontinuous) values – No Analogue

http://www.youwall.com/index.php?ver=NDAwNg==

^ Tocci, R. 2006. Digital Systems: Principles and Applications (10th Edition). Prentice Hall. 
ISBN 0-13-172579-3
 So what --- What’s the use ?

Where can I apply the learned

knowledge?

Can I see “Digital System Design” in

action ?
Digital Systems….
 Wherever – you have discrete values to process…
 Micro-Processors….. Core i5, Core i7
 Digital Signal Processing
 Audio Processing – MP3 Players, Equalizers
 Image Processing – Cameras, Loads of Processing
 Sensing --- Medical Equipment
 Video Processing – Display Technologies, UHD Resolution,
Disparity Tracking…..
 Simple example : Face Focusing
 Communication – Mobile Phones, Smartphones…
 Endless List
[SHO]
What shall I learn in this course ?
 The Course…
12

 After successful completion of this course the students shall be

able to port complex algorithms to hardware by designing efficient
data-paths and controllers; and shall have the desired knowledge
to optimize design for meeting design specifications (speed, area,
timings)
 The related relevant courses in your stream are:
 ASIC Design Methodology
 Advanced VLSI System Design
 Course Outline
No Topic Description/ Lecture Breakdown
1 Introduction Outline & Introduction
Initial Assessment of students
Digital design methodology & design flow
2 Verilog+ Combinational Logic Review + Verilog Introduction
Combinational Logic Combinational Building Blocks in Verilog

3 Verilog + Sequential Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS)
Logic Sequential Logic in Verilog

4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements

5 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency,

Timing]
6 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]

7 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs
 Course Outline
Week Topic Description/ Lecture Breakdown
8 Cross Clock Domain (CDC) Cross-Clock Domain Issues & RESET circuits
Issues
9 Fixed-Point Arithmetic Arithmetic Operations: Review Fixed Point Representation
10 Adders Adders & Fast Adders
Multi-Operand Addition
11 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers
12 Selected topics
 Reference/Related Books
15

 (Sam) Verilog HDL, Samir Palnitkar

 (Cil) Advanced Digital Design with the Verilog HDL, M D. Ciletti
 (Sho) Digital Design of Signal Processing systems, Shoab Ahmed Khan
 Distribution
16

 Quizzes 15%
 Assignment + Project 5%
 Mid 30%
 Final 50%
 An Excellent Verilog Tutorial
17

 Verilog Tutorial
 http://www.asic-world.com/verilog/veritut.html
 Writing Technical Paper
 http://www1.cs.columbia.edu/~hgs/etc/writing-style.html
 Class Ethics &.. Other stuff
18

 Attendance
 Respect for all & classroom discipline
 Quizzes
 Announced
 “Never cheat”
 Better fail NOW or else will fail sometime LATER in life
 Assignments
 Plagiarism
 No copying
 PLAGIARISM

Adapted from What is Plagiarism PowerPoint

19 http://mciu.org/~spjvweb/plagiarism.ppt
Design Space Exploration
What’s the difference between
software & hardware ?
H/W vs. S/W

 What do you mean when you say your design is

S/W or H/W based?
 S/W is where we have instructions. Executed on
programmable H/W unit
 H/W is where we have a dedicated data-path
defined
 Ignore syntax in this slide !!
Example- Add 8 numbers

C Code Verilog Code

 Result myfunc (a,b,c,d,e,f,g,h)  my_verilog_module (
inputs: a,b,c,d,e,f,g,h
Outputs: Result)
 int a,b,c,d,e,f,r1,r2,r3,r4,rr1,rr2
 wire a,b,c,d,e,f,r1,r2,r3,r4,r5
 //a-h get values from somewhere
 ----------
 r1= a+b;
 r1= a+b;
 r2 = c+d;
 r2 = c+d;
 r3 = e+f;
 r3 = e+f;
 r4 = g+h
 r4 = g+h
 rr1 = r1+r2
 rr1 = r1+r2
 rr2= r3 + r4;
 rr2= r3 + r4;
 Result = rr1 + rr2;
 Result = rr1 + rr2
 What happens actually
C Code Verilog Code
 Gets sequentially  A datapath is created
executed on a processor  & its parallel & this is where
H/W benefit comes
c,d e,f g,h
a,b

Instructions Queue
r1= a+b;
r2 = c+d; ALU
r3 = e+f;
r4 = g+h
rr1 = r1+r2
rr2= r3 + r4;
Result = rr1 + rr2;

Memory
Controller
What is the design space for a
digital system designer ?
 Design Options/Space
26
 Programmable Processors (& Microcontrollers) [General purpose Instruction Set Processors ]
 Programming flexibility
 Optimized - Architectures with so much design effort put in their designs
 Examples: Intel, Atmel, ARM Processors
 Digital Signal Processors / [Application Specific Instruction Set Processors (ASIPs)]
 Programming flexibility. Optimized Architectures for DSP Applications e.g. dedicated MAC units
 Examples: DSP from Texas Instruments, Array/Vector instructions
 FPGA
 Reconfigurable Hardware
 Typically Fully dedicated design ----- Longer Development cycle
 ASIC
 Lower cost, low power, No flexibility
 Custom Application Specific Instruction Set Processors (ASIPs) such as DIGIC 4 OR Fully dedicated design
 Hybrid Architectures
 HW/SW combined designs
 FPGAs containing Processors Soft Processors [Microblaze, NIOS, Power PC]
 Processors Containing (tightly coupled with) reconfigurable (coarse/fine) logic
 Canon DIGIC 5+
Application Specific Instruction Set Processor

Application Specific Processors are

typically combination of an
instruction programmable core
with specialized hardware units.

http://thenewcamera.com/wp-content/uploads/2012/01/Canon-1D-X-processing-syste.jpg
http://www.dancewithshadows.com/tech/wp-content/uploads/2009/03/canon-eos-t1i-photo.jpg
 DIGIC 5+
The most recent version, DIGIC 5, was
co-designed by Texas Instruments and
based on the Texas Instruments OMAP, a 
System-on-Chip (SoC) that includes an 
ARM architecture processor.[1][2] Since
these processors are based around the 
ARM CPUs, custom firmware for these
units have been developed to add
features to the cameras.

Source Wikipedia
 Post Fabrication
The future….. reconfigurable
Enhancements
Hybrid Architectures

Cash the benefit of both…

• Easy & Rapid Development
• Customized H/W only for compute
intensive units

Xilinx
ZYNQ 7000
 Design Space Options
30

Application
Specific
Custom
Dedicated
Design

[SHO]
How to select the best from the
design space ?
 Design Decision depends on the nature &
complexity of applications
32

 Applications are
characterized by amount
of data, parallelism, real
time requirements.
 And..
 Time to market
 Cost
 Complexity to port to H/W
 Quantity
 Power Requirements
 A typical system
33

 For complex systems

HW/SW co design may be
the only optimal choice.
 Soft processors like NIOS
even allow you to make
custom instructions !
 Use a processor with
FPGA/ASICS as Hardware
Accelerators
 Reading Assignment
34

 http://www.design-reuse.com/articles/9010/fp
ga-s-vs-asic-s.html
 FPGA's vs. ASIC's
Questions….