Professional Documents
Culture Documents
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Version 3.00
Copyright 1995-1999 SCRA
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RASSP
Reinventing
Rapid Prototyping Design
Process
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
HW HW
DESIGN FAB
SYSTEM FUNCTION HW & INTEG.
DEF. DESIGN SW & TEST
PART.
SW SW
HW & SW
DESIGN CODE
CODESIGN
HW & SW
Partitioning
& Codesign
Copyright 1995-1999 SCRA 2
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Goals
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
HW and SW Synthesis Methodologies
Industry Approaches to HW/SW Codesign
Hardware/Software Codesign Research
Summary
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
HW and SW Synthesis Methodologies
Industry Approaches to HW/SW Codesign
Hardware/Software Codesign Research
Summary
RASSP
Reinventing
Codesign Definition
and Key Concepts
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Codesign
The meeting of system-level objectives by exploiting
the trade-offs between hardware and software in a
system through their concurrent design
Key concepts
Concurrent: hardware and software developed at the
same time on parallel paths
Integrated: interaction between hardware and software
development to produce design meeting performance
criteria and functional specs
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Motivations for Codesign
DARPA Tri-Service
RASSP
Reinventing
Motivations for Codesign
(cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Categorizing
Hardware/Software Systems
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Application Domain
Embedded systems
Manufacturing control
Consumer electronics
Vehicles
Telecommunications
Defense Systems
Instruction Set Architectures
Reconfigurable Systems
Degree of programmability
Access to programming
Levels of programming
Implementation Features
Discrete vs. integrated components
Fabrication technologies
RASSP
Reinventing
Categories of Codesign
Problems
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Codesign of ISAs
Application-specific
instruction set processors (ASIPs)
Compiler and hardware optimization and trade-offs
RASSP
Reinventing
Components of the Codesign
Problem
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Embedded Systems
DARPA Tri-Service
Embedded Systems
Application-specific systems which contain hardware
and software tailored for a particular task and are
generally part of a larger system (e.g., industrial
controllers)
Characteristics
Are dedicated to a particular application
Include processors dedicated to specific functions
Represent a subset of reactive (responsive to external
inputs) systems
Contain real-time constraints
Include requirements that span:
Performance
Reliability
Form factor
Copyright 1995-1999 SCRA 1
Methodology
RASSP
Reinventing
Embedded Systems:
Specific Trends
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Embedded Systems:
Examples
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Embedded Systems:
Complexity Issues
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Techniques to Support
Complexity Management
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Description languages
Simulation
Standards
Design methodology management framework
RASSP
A Model of the Current
Reinventing
Electronic
Design
Hardware/Software Design
Process
Architecture Infrastructure
DARPA Tri-Service
DOD-STD-2167A
HWCI
HW Development Testing
Fabric.
Detailed
Design
Prelim.
Design
Hardware
Require.
Sys/HW
Analysis
Require.
Analysis
System System Operation.
Concepts Integ. and Testing and
Sys/SW test Eval.
Require.
Analysis Software
Require.
Analysis Prelim.
Design
Detailed
Design
Coding,
Unit test.,
SW Development Integ. test CSCI
Testing
Copyright 1995-1999 SCRA © IEEE 1991 [Franke91] 1
Methodology
RASSP
Reinventing
Current Hardware/Software
Design Process
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Incorrect Assumptions in
Reinventing
Electronic
Design
Current Hardware/Software
Design Process
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Directions of the HW/SW
Design Process
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Requirements for the Ideal
Codesign Environment
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Requirements for the Ideal
Codesign Environment (cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Cross-fertilization Between
Reinventing
Electronic
Design
Hardware and Software
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Cross-fertilization Between
Reinventing
Electronic
Design
Hardware and Software
Design (cont.)
Architecture Infrastructure
DARPA Tri-Service
VLSI SOFTWARE
DESIGN ENGINEERING
Graphics-driven design
RASSP
Cross-fertilization Between
Reinventing
Electronic
Design
Hardware and Software
Design (cont.)
Architecture Infrastructure
DARPA Tri-Service
SOFTWARE VLSI
ENGINEERING DESIGN
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Typical Codesign Process
DARPA Tri-Service
System
FSM- Description Concurrent processes
directed graphs (Functional) Programming languages
SW HW
Another
HW/SW Software Interface Hardware
Synthesis Synthesis Synthesis
partition
RASSP
Reinventing
Conventional Codesign
Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Analysis of Constraints
and Requirements
System Specs..
HW/SW
Partitioning
HW/SW Integration
and Cosimulation
Integrated
System © IEEE 1994
System Evaluation Design Verification
Copyright 1995-1999 SCRA
[Rozenblit94] 2
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Codesign Features
DARPA Tri-Service
RASSP
Reinventing
State of Codesign
Technology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Possible solutions:
Extend existing hardware/software languages to the use
of heterogeneous paradigms
Extend formal verification techniques to the HW/SW
domain
RASSP
Reinventing
Issues and Problems:
Integration
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
3
Cost / Instr.
Relative
2
Prog.
1 Folklore
25 50 75 100
% Util. of speed and mem capacity
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
RASSP
Reinventing
Unified HW/SW
Representation
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Unified Representation --
A representation of a system that can be used to
describe its functionality independent of its
implementation in hardware or software
Allows hardware/software partitioning to be delayed
until trade-offs can be made
Typically used at a high-level in the design process
RASSP
Current Abstraction
Reinventing
Electronic
Design
Mechanisms in
Hardware Systems
Architecture Infrastructure
DARPA Tri-Service
Abstraction
The level of detail contained within the system model
RASSP
Reinventing
Abstractions in Modeling:
Hardware Systems
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Current Abstraction
Reinventing
Electronic
Design
Mechanisms for
Software Systems
Architecture Infrastructure
DARPA Tri-Service
Virtual machine
A software layer very close to the hardware that hides
the hardware’s details and provides an abstract and
portable view to the application programmer
Attributes
Developer can treat it as the real machine
A convenient set of instructions can be used by
developer to model system
Certain design decisions are hidden from the
programmer
Operating systems are often viewed as virtual machines
RASSP
Reinventing
Abstractions for
Software Systems
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
• Application Programs
• Utility Programs
• Operating System
• Monitor
• Machine Language
• Microcode
• Logic Devices
RASSP
Reinventing
Abstract Hardware-Software
Model
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Abstract Evaluation
Identification
HW/SW of Design
of Bottlenecks
Model Alternatives
Evaluation
of HW/SW
Trade-offs
RASSP
Reinventing
Examples of Unified HW/SW
Representations
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Unified Representations
(Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
5 X 4 Y
Example:
+ + Control Step 1
+ Control Step 2
+ Control Step 3
RASSP
Reinventing
Unified Representations
(Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Concurrent processes
Interactive processes executing concurrently with other
processes in the system-level specification
Enable hardware and software modeling
RASSP
Reinventing
Unified Representations
(Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Object-oriented representations:
Use techniques previously applied to software to
manage complexity and change in hardware modeling
Use C++ to describe hardware and display OO
characteristics
Use OO concepts such as
Data abstraction
Information hiding
Inheritance
Use building block approach to gain OO benefits
Higher component reuse
Lower design cost
Faster system design process
Increased reliability
Copyright 1995-1999 SCRA 4
Methodology
RASSP
Reinventing
Unified Representations
(Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Object-oriented representation
Example:
3 Levels of abstraction:
RASSP
Reinventing
Unified Representations
(Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Example:
Input Token
Places
Transition
Output
Place
Copyright 1995-1999 SCRA 4
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
RASSP
Reinventing
Hardware/Software
Partitioning
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Definition
The process of deciding, for each subsystem, whether
the required functionality is more advantageously
implemented in hardware or software
Goal
To achieve a partition that will give us the required
performance within the overall system requirements (in
size, weight, power, cost, etc.)
This is a multivariate optimization problem that
when automated, is an NP-hard problem
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
HW/SW Partitioning Issues
DARPA Tri-Service
Software implementation
May run on high-performance processors at low cost
(due to high-volume production)
Incurs high cost of developing and maintaining
(complex) software
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Partitioning Approaches
DARPA Tri-Service
RASSP
Reinventing
System Partitioning
(Functional Partitioning)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Partitioning Metrics
DARPA Tri-Service
RASSP
Reinventing
Binding Software
to Hardware
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Hardware/Software System
Architecture Trends
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
HW/SW Partition
Formal Definition
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Performance Satisfying
Partition
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Issues in Partitioning
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Issues in Partitioning (Cont.)
DARPA Tri-Service
Component allocation
Output
Copyright 1995-1999 SCRA 5
Methodology
RASSP
Reinventing
Specification Abstraction
Levels
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Specification Abstraction
Levels (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Register transfers
The transfers between registers for each machine state
are described
Structure
A structural interconnection of physical components
Often called a netlist
RASSP
Reinventing
Granularity Issues in
Partitioning
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
System Component
Allocation
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Metrics and Estimations
Issues
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Metrics in HW/SW Partitioning
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Computation of Metrics
DARPA Tri-Service
RASSP
Reinventing
Objective and Closeness
Functions
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
+ k2 * F(delay, delay_constr)
+ k3 * F(power, power_constr)
Copyright 1995-1999 SCRA 6
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Partitioning Algorithm Issues
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Partitioning Algorithm Classes
DARPA Tri-Service
Constructive algorithms
Group objects into a complete partition
Use closeness metrics to group objects, hoping for a
good partition
Spend computation time constructing a small number
of partitions
Iterative algorithms
Modify a complete partition in the hope that such
modifications will improve the partition
Use an objective function to evaluate each partition
Yield more accurate evaluations than closeness
functions used by constructive algorithms
In practice, a combination of constructive and
iterative algorithms is often employed
Copyright 1995-1999 SCRA 6
Methodology
RASSP
Reinventing
Iterative Partitioning
Algorithms
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
B
A, B - Local minima
A
C - Global minimum
C
Copyright 1995-1999 SCRA 6
Methodology
RASSP
Reinventing
Iterative Partitioning
Algorithms (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Output Issues in Partitioning
DARPA Tri-Service
RASSP
Reinventing
Flow of Control and
Designer Interaction
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Comparing Partitions Using
Cost Functions
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Cosimulation
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Verilog Cosimulation Example
DARPA Tri-Service
Verilog HW Simulator
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
VHDL Cosimulation Example
DARPA Tri-Service
VHDL Simulator
Allowing hardware
SW
simulation models to
VHDL Foreign Language proc 1 “cosimulate” with software
Interface processes.
SW
proc 2
RASSP
Reinventing
Electronic
Design
Cosimulation for DSP
Multicomputer Application
Architecture Infrastructure
DARPA Tri-Service
Algorithm - C
Architecture - VHDL
Scheduler - C
CPU
CPU11 CPU
CPU22 CPU
CPU33 CPU
CPU44
Mapping Function (e.g.):
Round Robin
Computational
Requirements Based
Communications
Communications
Communications Network
Network
Requirements Based
RASSP
Reinventing
Electronic
Design
Cosimulation for DSP
Multicomputer Application
Architecture Infrastructure
DARPA Tri-Service
Send(destination, message_length)
Recv(source, message_length)
Compute(time)
Copyright 1995-1999 SCRA 7
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Model Continuity Problem
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
RASSP
Reinventing
Hardware Design
Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Preliminary Detailed
Hardware
Hardware Hardware Fabrication Testing
Requirements
Design Design
RASSP
Reinventing
Hardware Design
Methodology (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Hardware Synthesis
DARPA Tri-Service
Definition
The automatic design and implementation of hardware
from a specification written in a hardware description
language
Goals/benefits
To quickly create and modify designs
To support a methodology that allows for multiple
design alternative consideration
To remove from the designer the handling of the
tedious details of VLSI design
To support the development of correct designs
Copyright 1995-1999 SCRA 8
Methodology
RASSP
Reinventing
Hardware Synthesis
Categories
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Algorithm synthesis
Synthesis from design requirements to control-flow
behavior or abstract behavior
Largely a manual process
Register-transfer synthesis
Also referred to as “high-level” or “behavioral”
synthesis
Synthesis from abstract behavior, control-flow
behavior, or register-transfer behavior (on one hand) to
register-transfer structure (on the other)
Logic synthesis
Synthesis from register-transfer structures or Boolean
equations to gate-level logic (or physical
implementations using a predefined cell or IC library)
Copyright 1995-1999 SCRA 8
Methodology
RASSP
Reinventing
Hardware Synthesis
Process Overview
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Specification Implementation
Verification
Gate-level Gate-level Gate
Simulation Analysis
Silicon Vendor
Layout
Place and Route
RASSP
Reinventing
Software Design
Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Software Software
Coding Testing Maintenance
Requirements Design
RASSP
Reinventing
Software Design
Methodology (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Software Synthesis
DARPA Tri-Service
RASSP
Reinventing
Why Use
Software Synthesis?
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Software Synthesis
Categories
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Language compilers
ADA and C compilers
Visual Basic
Domain-specific synthesis
Application generators from software libraries
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Software Synthesis Examples
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
GrTT Tool Architecture
DARPA Tri-Service
Behavior GRAPH
ANALYSIS
Behavioral Specification
Code
Fragments
AUTOCODER
Ada Source
Code File
MCCI Domain Primitive Database
Copyright 1995-1999 SCRA 9
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Interface Synthesis
DARPA Tri-Service
RASSP
Reinventing
Interface Synthesis
Approaches
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
serial port
parallel port
self-timed
synchronous
blocking
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Cosynthesis
DARPA Tri-Service
RASSP
Reinventing
Cosynthesis Approach to
System Implementation
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
System
Input
Behavioral
Memory Specification and
Performance criteria System
Output
Mixed
Implementation
Pure HW
Performance
Pure SW Constraints
Cost [Gupta93] 9
Copyright 1995-1999 SCRA © IEEE 1993
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
HW and SW Synthesis Methodologies
RASSP
Reinventing
Sanders Codesign
Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Global influences
Design Tool Virtual Cost
Libraries
rules select. Environ. models
SW Req.
Feedback Partition. Design Code
At all Test
to user
steps
Integrate System
HW/SW Integrated HW/SW & Test Checkout
Req. Algorithm Tradeoff Simulation
Analysis Develop. Analysis
Fab &
HW Req. Logical Anal. Test
Requirements Partition. & Phys. &
Design Simul.
Hardware Modules
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Methodology
DARPA Tri-Service
Integrated Modeling Substrate
System
Requirements
Arch Ind.
Proc Model
Hardware Software
Perf. Model Perf. Model
S Arch Dep.
Behavior I
Level Model L Proc Model
M I
U B
ISA L R Source Code
Model A A
T R HOL
I Y
RTL Model O
Assembly
N
Gate Level
Model
Prototype Load
Hardware Module
Copyright 1995-1999 SCRA
[RASSP94] 9
Methodology
RASSP
Reinventing
Sanders Codesign
Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Subsystems process
Processingrequirements are modeled in an architecture-
independent manner
Codesign not an issue
Architecture process
HW/SW allocation analyzed via modeling of SW
performance on candidate architectures
Hierarchical verification is performed using finer grain
modeling (ISA and below)
Detailed design
Downloadable executable application and test code is
verified to maximum extent possible
Library support
SW models validated on test data
HW models validated using existing SW models
HW & SW models jointed iterated throughout designs
Copyright 1995-1999 SCRA 9
Methodology
RASSP
Reinventing
Lockheed Martin ATL
Codesign Methodology
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
SW Req. SW SW SW
Spec. Design Code Debug
Partition.
SW
Prototype Test
User
Req. Top Interface
HW/SW HW/SW
& level
Tradeoff Cosimul.
Spec. Arch. HW/SW System
Integ. Checkout
Algor. HW
develop. Sim.
& simul.
HW HW
HW HW
Spec.. Dev.
Design Test
Partition
HW
Anal.
& Fab
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
HW and SW Synthesis Methodologies
Industry Approaches to HW/SW Codesign
RASSP
Reinventing
Major Codesign Research
Efforts
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Chinook
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Cosmos
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Cosyma
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Polis
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Ptolemy
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Siera
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Chinook
DARPA Tri-Service
RASSP
Reinventing
Chinook’s Principal
Innovations
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
The Chinook System
DARPA Tri-Service
parser
parser scheduler
scheduler
program
Verilog
Specification
comm.
comm. code
code
synthesizer
synthesizer generator
generator
driver
driver interface
interface
synthesizer
synthesizer synthesizer
synthesizer
Processor &
Device Libraries netlist
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Chinook
DARPA Tri-Service
(Unified Representation)
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Scheduling in Chinook
DARPA Tri-Service
RASSP
Reinventing
Interface Synthesis in
Chinook
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Communications Synthesis
Reinventing
Electronic
Design
and System Simulation in
Chinook
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Cosynthesis of Embedded
Applications (COSYMA)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
COSYMA (Cont.)
DARPA Tri-Service
RASSP
Reinventing
Design Flow in a
COSYMA System
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
C* Mode
Simulator
C* Compiler
ES to C ES Flowgraph ES to HW C
C Compiler Cost
Estimation Olympus
Run time
Object Code
Analysis
Copyright 1995-1999 SCRA 1
Methodology
RASSP
Reinventing
COSYMA - Aims and
Strategies
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
COSYMA - Cost Function
and Metrics
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
COSYMA - Cost Function and
Metrics (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Ptolemy
DARPA Tri-Service
Attributes
Facilitatesmixed-mode system simulation,
specification, and design
Supports generation of DSP assembly code from a
block diagram description of algorithm
Uses object-oriented representations to model
subsystems efficiently
Supports different design styles called domains
RASSP
Reinventing
Codesign Methodology
Using Ptolemy
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Codesign Methodology
Using Ptolemy (Cont.)
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Netlist
Generation Ptolemy
VHDL/Synopsys
Simulation
© IEEE 1994
System
System Layout + Software
Copyright 1995-1999 SCRA [Rozenblit94] 1
Ptolemy Heterogeneous
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Simulation Environment
DARPA Tri-Service
Structural Components
Universe
(Ptolemy Simulation Kernel)
Geodesic
Plasma
Separate Model of Computation Separate Model of Computation
(e.g. discrete event) (e.g. data flow)
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
POLIS
DARPA Tri-Service
RASSP
Reinventing
POLIS
Unified Representation
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Codesign Finite State
Machines
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
(*Key == Off) or
(*Belt == On) (*End == 5) *Alarm = On
Off
(*End == 10) or
Alarm
(*Belt == On) or
(*Key == Off) *Alarm = Off
Copyright 1995-1999 SCRA 1
Methodology
RASSP
Reinventing
S-graph Software
Specification
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Begin
Next
S==Off
True False
*Key==On S==Wait
False
True False True
*Start *END==5 *END==10
False
Next True False True
S=Wait *Key==Off *Alarm=On *Belt==On
False
Next Next False True
True
*Belt==On S=Alarm *Key==Off
True True
False Next False
*Alarm=Off
Next
S=Off
Next
End
RASSP
Reinventing
Partitioning and Scheduling in
POLIS
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Interfaces Among Partitions
DARPA Tri-Service
Sender A B C Receiver
Example HW to SW interface
ack
HW HW to SW SW
X y
-1 / 0
11 + 0- / 0
X
0 1 -0 / 1
y
ack
Copyright 1995-1999 SCRA 10 / 1 x ack / y 1
Methodology
RASSP
Reinventing
The POLIS Co-design
Environment
Electronic
Design
Architecture Infrastructure
DARPA Tri-Service
Formal
Verification
Compilers
Partitioning
CFSMs
SW Synthesis HW Synthesis
Interface
Synthesis
Prototype
Copyright 1995-1999 SCRA 1
Methodology
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Outline
DARPA Tri-Service
Introduction
Unified HW/SW Representations
HW/SW Partitioning Techniques
Integrated HW/SW Modeling Methodologies
HW and SW Synthesis Methodologies
Industry Approaches to HW/SW Codesign
Hardware/Software Codesign Research
Summary
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
Module Summary
DARPA Tri-Service
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
References
DARPA Tri-Service
[Boehm73] Boehm, B.W. “Software and its Impact: A Quantitative Assessment,” Datamation, May
1973, p. 48-59.
[Buchenrieder93] Buchenrieder, K., “Codesign and Concurrent Engineering”, Hot Topics, IEEE
Computer, R. D. Williams, ed., January, 1993, pp. 85-86
[Buck94] Buck, J., et al., “Ptolemy: a Framework for Simulating and Prototyping Heterogeneous
Systems,” International Journal of Computer Simulation, Vol. 4, April 1994, pp. 155-182.
[Chiodo92] Chiod0, M., A. Sangiovanni-Vincentelli, “Design Methods for Reactive Real-time Systems
Codesign,” International Workshop on Hardware/Software Codesign, Estes Park, Colorado,
September 1992.
[Chiodo94] Chiodo, M., P. Giusto, A. Jurecska, M. Marelli, H. C. Hsieh, A. Sangiovanni-Vincentelli, L.
Lavagno, “Hardware-Software Codesign of Embedded Systems,” IEEE Micro, August, 1994, pp. 26-
36; © IEEE 1994.
[Chou95] P. Chou, R. Ortega, G. Borriello, “The Chinook hardware/software Co-design System,”
Proceedings ISSS, Cannes, France, 1995, pp. 22-27.
[DeMicheli93] De Micheli, G., “Extending CAD Tools and Techniques”, Hot Topics, IEEE Computer, R.
D. Williams, ed., January, 1993, pp. 84
[DeMicheli94] De Micheli, G., “Computer-Aided Hardware-Software Codesign”, IEEE Micro, August,
1994, pp. 10-16
[DeMichelli97] De Micheli, G., R. K. Gupta, “Hardware/Software Co-Design,” Proceedings of the IEEE,
Vol. 85, No. 3, March 1997, pp. 349-365.
[Ernst93] Ernst, R., J. Henkel, T. Benner, “Hardware-Software Cosynthesis for Micro-controllers”, IEEE
Design and Test, December, 1993, pp. 64-75
[Franke91] Franke, D.W., M.K. Purvis. “Hardware/Software Codesign: A Perspective,” Proceedings of
the 13th International Conference on Software Engineering, May 13-16, 1991, p. 344-352; © IEEE
1991
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
References (Cont.)
DARPA Tri-Service
[Gajski94] Gajski, D. D., F. Vahid, S. Narayan, J. Gong, Specification and Design of Embedded
Systems, Prentice Hall, Englewood Cliffs, N J, 07632, 1994
[Gupta92] Gupta, R.K., C.N. Coelho, Jr., G.D. Micheli. “Synthesis and Simulation of Digital Systems
Containing Interactive Hardware and Software Components,” 29th Design Automation Conference,
June 1992, p.225-230.
[Gupta93] Gupta, R.K., G. DeMicheli, “Hardware-Software Cosynthesis for Digital Systems,” IEEE
Design and Test, September 1993, p.29-40; © IEEE 1993.
[Hermann94] Hermann, D., J. Henkel, R. Ernst, “An approach to the estimation of adapted Cost
Parameters in the COSYMA System”, 3rd International Conference on Hardware/Software
codesign, Grenoble, France, September 22-24, 1994, pp. 100-107
[Hood94] Hood, W., C. Myers, "RASSP: Viewpoint from a Prime Developer," Proceedings 1st Annual
RASSP Conference, Aug. 1994.
[IEEE] All referenced IEEE material is used with permission.
[Ismail95] T. Ismail, A. Jerraya, “Synthesis Steps and Design Models for Codesign,” IEEE Computer,
no. 2, pp. 44-52, Feb 1995.
[Kalavade93] A. Kalavade, E. Lee, “A Hardware-Software Co-design Methodology for DSP
Applications,” IEEE Design and Test, vol. 10, no. 3, pp. 16-28, Sept. 1993.
[Klenke96] Klenke, R. H., J. H. Aylor, R. Hillson, D. J. Kaplan, “VHDL-Based Performance Modeling for
the Processing Graph Method Tool (PGMT) Environment,” Proceedings of the VHDL International
Users Forum, Spring 1996, pp. 69-73.
[Kumar95] Kumar, S., “A Unified Representation for Hardware/Software Codesign”, Doctoral
Dissertation, Department of Electrical Engineering, University of Virginia, May, 1995
[Jalote91] Jalote, P., An Integrated Approach to Software Engineering, Springer-Verlag, New York,
1991.
[McFarland90] McFarland, M.C., A.C. Parker, R. Camposano. “The High-Level Synthesis of Digital
Systems,” Proceedings of the IEEE, Vol. 78, No. 2, February 1990, p.301-318, © IEEE 1990.
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
References (Cont.)
DARPA Tri-Service
[Parker84] Parker, A.C., “Automated Synthesis of Digital Systems,” IEEE Design and Test,, November
1984, p. 75-81.
[RASSP94] Proceedings of the 1st RASSP Conference, Aug. 15-18, 1994.
[Rozenblit94] Rozenblit, J. and K. Buchenrieder (editors). Codesign Computer -Aided
Software/Hardware Engineering, IEEE Press, Piscataway, NJ, 1994; © IEEE 1994.
[Smith86] Smith, C.U., R.R. Gross. “Technology Transfer between VLSI Design and Software
Engineering: CAD Tools and Design Methodologies,” Proceedings of the IEEE, Vol. 74, No. 6, June
1986, p.875-885.
[Srivastava91] M. B. Srivastava, R. W. Broderson, “Rapid prototyping of Hardware and Software in a
Unified Framework,” Proceedings ICCAD, 1991, pp. 152-155.
[Subrahmanyam93] Subrahmanyam, P. A., “Hardware-Software Codesign -- Cautious optimism for the
future”, Hot Topics, IEEE Computer, R. D. Williams, ed., January, 1993, pp. 84
[Tanenbaum87] Tanenbaum, A.S., Operating Systems: Design and Implementation, Prentice-Hall, Inc.,
Englewood Cliffs, N.J., 1987.
[Terry90] Terry, C. “Concurrent Hardware and Software Design Benefits Embedded Systems,” EDN,
July 1990, p. 148-154.
[Thimbleby88] Thimbleby, H. “Delaying Commitment,” IEEE Software, Vol. 5, No. 3, May 1988, p. 78-86.
[Thomas93] Thomas, D.E., J.K. Adams, H. Schmitt, “A Model and Methodology for Hardware-Software
Codesign,” IEEE Design and Test, September 1993, p.6-15; © IEEE 1993.
[Turn78] Turn, R., “Hardware-Software Tradeoffs in Reliable Software Development,” 11th Annual
Asilomar Conference on Circuits, Systems, and Computers, 1978, p.282-288.
[Vahid94] Vahid, F., J. Gong, D. D. Gajski, “A Binary Constraint Search Algorithm for Minimizing
Hardware During Hardware/Software Partitioning”, 3rd International Conference on
Hardware/Software Codesign, Grenoble, France, Sepetember22-24, 1994, pp. 214-219
[Wolf94] Wolf, W.H. “Hardware-Software Codesign of Embedded Systems,” Proceedings of the IEEE,
Vol. 82, No.7, July 1994, p.965-989.
RASSP
Reinventing
Electronic
Design
Architecture Infrastructure
References (Cont.)
DARPA Tri-Service
Additional Reading:
Aylor, J.H. et al., "The Integration of Performance and Functional Modeling in VHDL” in Performance
and Fault Modeling with VHDL, J. Schoen, ed., Prentice-Hall, Englewood Cliffs, N.J., 1992.
D’Ambrosio, J. G., X. Hu, “Configuration-level Hardware-Software Partitioning for Real-time Embedded
Systems”, 3rd International Conference on Hardware/Software codesign, Grenoble, France,
September 22-24, 1994, pp. 34-41
Eles, P., Z. Peng, A. Doboli, “VHDL System-Level Specification and Partitioning in a Hardware-Software
Cosynthesis Environment”, 3rd International Conference on Hardware/Software codesign,
Grenoble, France, September 22-24, 1994, pp. 49-55
Gupta, R.K., G. DeMicheli, “Hardware-Software Cosynthesis for Digital Systems,” IEEE Design and
Test, September 1993, p.29-40.
Richards, M., Gadient, A., Frank, G., eds. Rapid Prototyping of Application Specific Signal Processors,
Kluwer Academic Publishers, Norwell, MA, 1997
Schultz, S.E., “An Overview of System Design,” ASIC and EDA, January 1993, p.12-21.
Thomas, D. E, J. K. Adams, H. Schmit, “A Model and Methodology for Hardware-Software Codesign”,
IEEE Design and Test, September, 1993, pp. 6-15
Zurcher, F.W., B. Randell, “Iterative Multi-level Modeling - A Methodology for Computer System
Design,” Proceedings IFIP Congress ‘68, Edinburgh, Scotland, August 1968, p.867-871.