Microcomputer Systems 1

Introduction to Blackfin DSP’s

Basic Processor Architectures
Von Neumann Architecture

Memory:
Memory: Address
AddressBus
Bus
Data
Data&& CPU
CPU
Instructions
Instructions Data
DataBus
Bus

Harvard Architecture

Program
Program PM
PMAddress
AddressBus
Bus
DM
DMAddress
AddressBus
Bus Data
Data
Memory:
Memory: CPU
CPU Memory:
Memory:
Instructions
Instructions PM
PMData
DataBus
Bus
DM
DMData
DataBus
Bus Data
Data

Modified Harvard Architecture

Program
Program PM
PMAddress
AddressBus
DM
DMAddress
AddressBus
Bus Data
Data
Instruction

Bus
Cache

Memory:
Memory: CPU
CPU Memory:
Memory:
Instructions
Instructions PM
PMData
DataBus
Bus
DM
DMData
DataBus
Bus Data
Data
09/23/21 Veton Këpuska 2
Blackfin Processor Architecture
The Blackfin architecture was crafted with the
requirements of a Controller and a DSP in mind

 16/32-bit Embedded Processor

 Processor designed for high signal processing performance.
 Utilizes RISC programming model.
 Hardware is based on Micro Signal Architecture (MSA) –
developed jointly by Intel Corporation and Analog Devices.
 MSA combines 32-bit RISC instruction set,
 16-bit fixed-point dual multiply-accumulate (MAC) digital signal
processing functionality
 8-bit video processing through four 8-bit ALUs
 Unified architecture provides both Microcontroller (MCU) & DSP
functionality.

09/23/21 Veton Këpuska 3

Blackfin Features
 Ethernet, CAN (Controller Area Network), GPIO
(General purpose Programmable Input Output), SPI
(Serial Peripheral Interface), USB (Universal Serial
Bus), UART (Universal Asynchronous Receiver
Transmitter), TWI (Twin Wire Interface, RTC (Real
Time Clock), SPORT (Serial Ports), Timers,
Watchdog
 Optimized to perform EQUALLY well on both control
and/or numeric algorithms
 Dynamic Power Management
 “Glueless” interface to many converter devices or
LCDs through Parallel Peripheral Interface (PPI)

09/23/21 Veton Këpuska 4

Representation of
Numbers & Arithmetic

Number Systems
Time Quantization (Sampling) of
Analog Signals
a) b) Analog-to-Digital
1 Conversion.
f s=
T a) Continuous
Signal x(t).
x(t)
b) Sampled signal
Analog
Low-pass
Sample
and x a ( nT ) with sampling
Filter period T
Hold
satisfying
Nyquist rate as
specified by
Sampling
Theorem.
Analog to
Digital x [ n] DSP
Converter
Converter c) Digital sequence
obtained after
sampling and
c) quantization x[n]

09/23/21 Veton Këpuska 6

Fixed-Point vs Floating Point DSP’s
 Fixed-Point DSP’s
 Numbers represented as 16/32 bits:
 216=65,536 or 232=4,294,967,296 bit patterns.
1. Unsigned Integer Format
 Stored Value:
16-bit: (0..65,536) or
32-bit: (0..4,294,967,296)
2. Signed Integer Format
 Stored Value:
16-bit: (-32,768..32,767) or
32-bit: (-2,147,483,648..2,147,483647)
3. Unsigned Fractional Format
 Stored Value:
16-bit: (0..1) 65,536 levels or
32-bit: (0..1) 4,294,967,296 levels
4. Signed Fractional Format
 Stored Value:
16-bit: (-1..1) 65,536 levels or
32-bit: (-1..1) 4,294,967,296 levels

09/23/21 Veton Këpuska 7

Blackfin Fixed-Point Representation
 ADI DSP’s including Blackfin use Fractional Format
Representation; 16-bit Example in 1.15 Format:
MSB LSB
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15

HEX BINARY DECIMAL

7FFF 0111 1111 1111 1111 +0.999969

0001 0000 0000 0000 0001 +0.000031

0000 0000 0000 0000 0000 +0.000000

FFFF 1111 1111 1111 1111 -0.000031

8000 1000 0000 0000 0000 -1.000000

09/23/21 Veton Këpuska 8

Blackfin Family DSPs
 Blackfin Processor Family –
Roadmap

Multiprocessor
• Symmetric Dual Core BF561 BF56x Family
• 328 kB RAM • 328 kB RAM
• 600+ MHz • DDR
• USB 2.0
• Integrated Peripherals • SATA
Performance

System Performance BF537

• 132 kB RAM
• Up to 756 MHz • CAN
BF533 • 10/100 Ethernet BF54x Family
• Integrated Peripherals • 148 kB RAM MAC • 328 kB RAM
• USB 2.0
• ATAPI
BF535 BF534 • CAN
• 308 kB RAM • 132 kB RAM • DDR
• USB • CAN
• PCI

BF536
• 100 kB RAM
• CAN
Portable–Low Power • 10/100
BF52x Family
• 132 kB RAM
• 400 MHz Ethernet • USB 2.0
• 0.23 mW/MHz MAC • 10/100 Ethernet MAC
BF532/BF531
• 84 kB RAM
• Multichip languages

Present Future

09/23/21 Veton Këpuska 10

Blackfin ADSP-BF535: For High-Performance
PCI-Connected Appliances
Performance 200MHz to 350MHz  Key Features
16/32-bit Core  Supports USB full-speed device
 PCI
 308Kbytes of on-board memory
 Dynamic Power Management varies frequency and
Power @ 1.5 V 600mW, 300 MHz voltage
@ 1.0 V 100mW, 100 MHz  Interfaces to external FLASH and SDRAM
Address Range 768 MBytes
On-Chip SRAM 308 Kbytes System Control Blocks
32-bit
Emulator Real
Instruction / Data Cache 48 Kbytes & Test
Event Watchdog Memory
Controllers Timer DMA
Time PLL
External
Bus
Control Clock Interface
On-Chip RAM 260 Kbytes
Peripherals PCI
USB Device Blackfin Core PCI v2.2
2 SPORTs Up to 350 MHz Master
/Slave
2 SPIs & 2 UARTs
3 32-bit Timers 16KB 32KB
Inst. Data L1
Voltage 1.0 V to 1.6 V SRAM / Cache
High Speed I/O
System Interface Unit

Temperature Range  0C to +70C Ambient L2 256 KB SRAM

-40C to +85C Ambient

Package 260 PBGA

USB v 1.1
SPORT0 SPORT1 GPIO TIMERS UART0 UART1
(16) (3) SPI0 SPI1 IrDA

09/23/21 Veton Këpuska 11

Summary of Blackfin BF531/2/3
DSP’s

ADSP-BF531
ADSP-BF531 ADSP-BF532
ADSP-BF532 ADSP-BF533
ADSP-BF533

400 MHz, 400 MHz, 500 / 600 / 756 MHz,

Performance
Performance 400 MHz, 400 MHz, 500 / 600 / 756 MHz,
800 MMACs 800 MMACs 1000 / 1200 / 1512 MMACs
800 MMACs 800 MMACs 1000 / 1200 / 1512 MMACs
On-Chip
On-Chip 52KBytes
KBytes 84KBytes
KBytes 148KBytes
148 KBytes
RAM 52 84
RAM
176 LQFP 176 LQFP
176 LQFP 176 LQFP 160MiniBGA
MiniBGA
176 Lead-free LQFP 176 Lead-free LQFP
Package
Package 176 Lead-free LQFP 176 Lead-free LQFP 160
160 MiniBGA 160 MiniBGA 160 Lead-free MiniBGA
Options 160 MiniBGA
160 Lead-free MiniBGA
160 MiniBGA
160 Lead-free MiniBGA
160 Lead-free MiniBGA
Options 160 Lead-free MiniBGA 160 Lead-free MiniBGA 169 Lead-free PBGA
169 Lead-free PBGA
169 Lead-free PBGA 169 Lead-free PBGA
169 Lead-free PBGA 169 Lead-free PBGA

09/23/21 Veton Këpuska 12

Blackfin Architecture
Blackfin Architecture Details
 Blackfin Core Details
 Registers
 ALU, MAC, Shifter
 Sequencer, Pipeline, Event Controller
 Blackfin Memory
 Memory Architecture
 Cache
 Peripherals
 General Peripherals:
 Parallel Peripheral Interface (PPI) Peripherals
Peripheralslisted
listedin
in
 Serial Ports (SPORTs) Blue are included in
Blue are included in
 Serial Peripheral Interface (SPI) BF531/532/533
BF531/532/533Family
Family
 General Purpose Timers
 Universal Asynchronous Receiver Transmitter (UART)
 Twin-Wire Interface (TWI)
 Real Time Clock (RTC)
 Watchdog Timer (WDT)
 Ethernet, CAN
 DMA
09/23/21 Veton Këpuska 14
Features
 Integrated instruction set architecture
 Single instruction set for signal processing and control
 Programmable interrupt levels
 Real-time tasks get the highest priority level
 Memory protection with an MMU
 Regions of memory can be protected from access
 Networked peripherals in addition high speed
connectivity to ADC, DAC and video peripherals
 Unified address space and byte addressable
 Support for User and Supervisor modes
 Robust ALU including both signal processing functions
as well as traditional MPC/MPU functions

09/23/21 Veton Këpuska 15

Blackfin ADSP-BF531/2/3
Architecture Overview
 Processor Core
 Registers
 ALU, MAC, Shifter
 Data Addressing Modes
 Program Sequencer
 Event Controller
 Peripherals
 Instruction Set Overview
 Memory
 Architecture
 Cache

09/23/21 Veton Këpuska 16

ADSP-BF533 Processor

09/23/21 Veton Këpuska 17

Processor Core Architecture
2 16-bit Multipliers
2 40-bit Arithmetic Logic Units (ALU)
2 40-bit Accumulators
1 40-bit Shifter
4 8-bit Video ALUs

Processor Unit Performs Operations

on

16 16 • 8-bit,
8 8 8 8
•16-bit, &
Barrel
Shifter
40 40 •32-bit data

ACC0 ACC1
From Register File:
8 32-bit Registers R0-R7

09/23/21 Veton Këpuska 18

Register File
Registers
 Blackfin processors are register-intensive
devices
 All computations are performed on data contained in
registers
 All peripherals are setup using registers
 Memory is accessed using pointers in address registers
 There are two types of Blackfin processor
registers
 Core registers
 Memory-Mapped Registers (MMRs)

09/23/21 Veton Këpuska 20

Blackfin Core Registers
 Core registers are accessed directly by name
 Data Registers: R0-R7
 Accumulator Registers: A0, A1
 Pointer Registers: P0-P5, FP, SP,USP
 Data Address Generator
DAG Registers: I0-I3, M0-M3, B0-B3, L0-L3
(Index, Modify, Base, Length registers – for circular buffers)
 Cycle Counters: CYCLES, CYCLES2
 Program Sequencer: SEQSTAT
 System Configuration
Register: SYSCFG
 Loop Registers: LT[1:0], LB[1:0], LC[1:0]
 Interrupt Return Registers: RETI, RETX, RETN, RETE

 Example (Assembly):
 R0 = SYSCFG; // Load data register with contents of
SYSCFG register
09/23/21 Veton Këpuska 21
Blacfin Core Registers
Data Registers 31 0
39 31 15 P0
A0X A0.H A0.L Address P1
A1.H A0.L P2
A1X Registers P3
31 15
R0 P4
R0.H R0.L
P5
R1 R1.H R1.L
FP
R2
SP
R3 USP
R4 R4.H R4.L 31 0 31 0 31 0 31 0
R5 I0 L0 B0 M0
I1 L1 B1 M1
R6
I2 L2 B2 M2
R7 R7.H R7.L I3 L3 B3 M3

ASTAT Arithmetic Status LC0

LT0 Loop Counter
RETS Subroutine Return LB0 Loop Top Shaded registers
Loop Bottom only accessible in
RETI Interrupt Return LC1 Supervisor mode
LT1
RETX Exception Return LB1
RETN NMI Return SYSCFG System Config
RETE Emulation Return SEQSTAT Sequencer Status

09/23/21 Veton Këpuska 22

Memory-Mapped Registers (MMR)
 A majority of registers are memory-mapped and must
be accessed indirectly
 Core MMRs are used to configure the core registers
 They are listed in Appendix A of the HRM: 892485982bf533_hwr.pdf
 All Core MMRs must be accessed with 32-bit reads or writes
 System MMRs are used to configure all other peripherals
 They are listed in Appendix B of the HRM: 892485982bf533_hwr.pdf
 Some System MMRs must be accessed with 32-bit reads or writes and
others with 16-bit reads or writes (See the HRM for details)
 MMR addresses are defined in header files
 defBF53x.h for assembly
 cdefBF53x.h for C/C++

 MMRs can only be accessed in Supervisor mode

09/23/21 Veton Këpuska 23

Code Examples
Assembly Example:
P0.H = HI(SPI_RDBR); // load upper 16-bits of SPI
// Receive Register address to
// pointer register
P0.L = LO(SPI_RDBR); // load lower 16-bits of SPI
// Receive Register address to
// pointer register
R0 = W[P0] (z); // read 16-bit SPI Receive Register
// (SPI_RDBR) into data register
Zero
ZeroExtended
Extended
C/C++ Example:
short temp; // define variable to store
// contents
temp = *pSPI_RDBR; // read 16-bit SPI Receive
// Register contents into data
// element

09/23/21 Veton Këpuska 24

Arithmetic Logic Units
Data Arithmetic Logic Unit
(ALU)
Data Arithmetic Unit

LD0 32-bits 16 16

8 8 8 8
R7 R7.H R7.L

R6 R6.H R6.L
LD1 32-bits
R5 R5.H R5.L

R4 R4.H R4.L barrel

40 40
R3 shifter
R3.H R3.L
SD 32-bits
R2 R2.H R2.L

R1 R1.H R1.L
A0 A1
R0 R0.H R0.L

09/23/21 Veton Këpuska 26

Arithmetic Logic Unit (ALU)
 Two 40-bit ALUs operate on 16-bit, 32-bit,
and 40-bit input data and output 16-bit,
32-bit, and 40-bit results.
 Functions
 Fixed-point addition and subtraction
 Addition and subtraction of immediate values
 Accumulation and subtraction of multiplier results
 Logical AND, OR, NOT, XOR, bitwise XOR (LFSR),
Negate
 Functions: ABS, MAX, MIN, Round, division primitives
 Supports conditional instructions
 Four 8-bit video ALUs

09/23/21 Veton Këpuska 27

Arithmetic Logic Unit (ALU)
 40-bit ALU operations support the
following combinations:
 Single 16-Bit Operations
 Dual 16-Bit Operations
 Quad 16-Bit Operations
 Single 32-Bit Operations
 Dual 32-Bit Operations

09/23/21 Veton Këpuska 28

Multiply Accumulators
(MAC)
Multiply Accumulators (MAC)
Data Arithmetic Unit

LD0 32-bits

16 16

8 8 8 8
LD1 32-bits
R7 R7.H R7.L
R6 R6.H R6.L

SD 32-bits R5 R5.H R5.L

R4 R4.H R4.L barrel
R3 R3.H 40 40
R3.L shifter
R2 R2.H R2.L
R1 R1.H R1.L
R0 R0.H R0.L A0 A1

09/23/21 Veton Këpuska 30

Multiply-Accumulate (MAC)
 Two identical MACs
 Each performs fixed-point multiplication and multiply-
accumulate operations on 16-bit fixed-point input data
and outputs 32-bit or 40-bit results.
 Functions
 Multiplication
 Multiply-accumulate with addition
 Multiply-accumulate with subtraction
 Dual versions of the above
 Features
 Saturation of accumulator results
 Optional rounding of multiplier results

09/23/21 Veton Këpuska 31

Barrel Shifter
Barrel Shifter
Data Arithmetic Unit

16 16

8 8 8 8

R7 R7.H R7.L
R6 R6.H R6.L
LD0 32-bits
R5 R5.H R5.L
R4 R4.H R4.L
R3 R3.H R3.L barrel
LD1 32-bits R2 R2.H R2.L shifter
40 40

R1 R1.H R1.L
R0 R0.H R0.L
SD 32-bits
A0 A1

09/23/21 Veton Këpuska 33

Barrel Shifter Functions
 Performs bitwise shifting for
 16-bit, 32-bit or 40-bit inputs and yields
 16-bit, 32-bit, or 40-bit outputs.

 Shift Functions
 Arithmetic Shifts preserve the sign of the original
number. The sign bit value back-fills the left-most bit
positions vacated by the arithmetic right shift.
 Logical Shifts discard any bits shifted out of the
register and back-fills vacated bits with zeros.

09/23/21 Veton Këpuska 34

Barrel Shifter Functions
 Additional Functions
 Rotate: Rotates a registered number through
the CC bit a specified distance and direction.

 Bit Operations – Set, Clear, Toggle, Test

 Field Extract and Deposit

09/23/21 Veton Këpuska 35

SEQSTAT Register
 The Sequencer Status register (SEQSTAT) contains information about
the current state of the sequencer as well as diagnostic information
from the last event. SEQSTAT is a read-only register and is accessible
only in Supervisor mode.

09/23/21 Veton Këpuska 36

Zero-Overhead Loop Registers
(LC, LT, and LB)
 Two sets of zero-overhead loop registers implement
loops, using hardware counters instead of software
instructions to evaluate loop conditions.
 After evaluation, processing branches to a new target
address. Both sets of registers include the
 Loop Counter (LC),
 Loop Top (LT), and
 Loop Bottom (LB) registers.

Registers Description Function

LC0, LC1 Loop Maintains a count of the remaining iterations of the loop

Counters
LT0, LT1 Loop Tops Holds the address of the first instruction within a loop

LB0, LB1 Loop Bottoms Holds the address of the last instruction of the loop

09/23/21 Veton Këpuska 37

SYSCFG Register
 The System Configuration register (SYSCFG) controls the
configuration of the processor. This register is accessible
only from the Supervisor mode.

09/23/21 Veton Këpuska 38

Interrupts vs. Exceptions
INTERRUPTS EXCEPTIONS
 Hardware-generated  Service Exception
 Asynchronous to program flow  Return address (RETE) is the
 Requested by a peripheral address following the excepting
instruction
 Software-generated
 Never re-executed
 Synchronous to program flow
 EXCPT instruction is in this
 Generated by RAISE category
instruction
 Error Condition Exception
 All instructions preceding
 Return address (RETE) is the
the interrupt in the pipeline address of the excepting
are killed instruction
 Excepting instruction will be re-
executed
The Blackfin is always in Supervisor Mode while
executing Event Handler software can be in User
Mode only while executing application tasks.
09/23/21 Veton Këpuska 39
Event Controller
 An interrupt is an event that changes
normal processor instruction flow and is
asynchronous to program flow.

 In contrast, an exception is a software

initiated event whose effects are
synchronous to program flow.

 The event system is nested and prioritized.

Consequently, several service routines may
be active at any time, and a low priority
event may be pre-empted by one of higher
priority.
09/23/21 Veton Këpuska 40
Processor Event Controller
 Processor Event Controller Consists of
2 stages:
 The Core Event Controller (CEC)
 System Interrupt Controller (SIC)

 Conceptually:
 Interrupts from the peripherals arrive at
SIC
 SIC routes interrupts directly to general-
purpose interrupts of the CEC.

09/23/21 Veton Këpuska 41

Core Event Controller (CEC)
 CEC supports
 9 general-purpose interrupts: IVG15-7
 IVG15-14 – 2 lowest priority interrupts for
software handlers.
 IRVG13-7 – 7 highest to support
peripherals.
 Additional dedicated interrupt and
exception events.

09/23/21 Veton Këpuska 42

System Interrupt Controller (SIC)
 SIC provides mapping and routing of
events:
 From: Peripheral interrupt sources
 To: Prioritized general-purpose interrupt
inputs of the CEC.
 Processor default mapping can be
altered by the user via Interrupt
Assignment Register (IAR).

09/23/21 Veton Këpuska 43

Interrupt Processing Block Diagram

It
8.
9.
7.
5.
6.
4.
1.
3.
2.
It should
When
When
The
ILAT
IMASK
The
SIC_ISR
SIC_IMASK
SIC_IWR
should be
the
the
Event
adds noted
masks
SIC_IARx
be event
interrupt
Vector
logs
noted that
Interrupt
off
the
masks
checks or
to
that emulation,
vector
service
Table for
(EVT)
Aemulation,
to
enables
registers,
request
off
see or its
which
and log
enables
ifforit isreset,
Interrupt
routine
events
should accessed
of
map
keeps ofA
(ISR)
the NMI,
interrupts
reset,wake has
interrupts for
toand
entered
different
track peripheral
NMI,up of from
the
and exception
Interrupt
look
latched up
core
systemcorethe
the
byAA
exception
8.
9.
7.
5.
6.
4.
1.
3.
2. When
When
The
ILAT
IMASK
The
SIC_ISR
SIC_IMASK
SIC_IWR the
the
Event
addsmasks
SIC_IARx event
interrupt
Vector
Interrupt
logs off
masks
checks vector
or service
Table
registers,
the to (EVT)
AInterrupt
to
enables
request
off
see or its
which
if Interrupt
routine
and logis
events
enables
it should accessed
of
map
keeps ofA
(ISR)
the has
interrupts for
toentered
different
track
interrupts
wake Interrupt
look
latched
peripheral
up of up
core
system
from
the corethethe
by
core
has
events, pipeline,
been
appropriate
the core
priorities.
as
interrupts
peripherals wellexecuted,
but
If
to as
that
at the
vector
not
the
anot appropriate
yet
IVGx
hardware
smaller
are the
for RTI
actively
event
set
asserted error
of IPEND
instruction
being A’s
corresponding
(IVHW)
general-purpose
but not bit
interrupt
serviced.
yet andis
clearsset,
is to
serviced thewhich
service
AAInterrupt
core timer
core(that AA
is,
from
core
has an
appropriate
the core
priorities.
events, as
interrupts
peripherals
from
clears
appropriate
routine
is not an
the
idled
pipeline,
been but
well If
to
that
idled atathe
state
the
executed,
vector
the
as
respective
(ISR).
masked, IPEND
system
yet
IVGxbased
appropriate
smaller
are
the
state
the
the
for
hardware
system
based
bit. ILAT
RTI
set
asserted
However,
process
level.
on
Interrupt
actively
event error
of
on
bit.
this
beingIf
IPEND
instruction
A’sInterrupt
interrupt
corresponding
(IVHW)
general-purpose
but
level.
this
Thus,
proceeds not
If bit
yet clears
interrupt
serviced.
and
Interrupt
interrupt
the IPEND
relevant
to Step
to
core
serviced is
request.
set, the
request.
tracks
not
iswhich
service
Interrupt
timer
core
SIC_ISR
7. (that
not
all is,
interrupts
an
(IVTMR) interrupt
masked,
clears
routine
is
an not interrupt
appropriate
interrupts the (IVG7
the
(ISR).
masked,
interrupt
masked, the service
request
IPEND
(IVG7 –
the
service–
request IVG15),
requests,
respective routine
proceeds
bit.ILAT enter
However,
process
IVG15),
routine
proceeds determine
hasn’t
bit. to
the
Thus,
proceeds yet
Step
interrupt
the
determine
hasn’tto yet
Step the
cleared
4.
IPEND
relevant
to Step
the
cleared
4. core
core thepriority
processing
tracks
SIC_ISR
7.the all
priority
(IVTMR)
pending interrupt requests, enter the interrupt processing
chain
bit
of
bit
ofat notinterrupts,
isisnot
Interrupt
interrupt).
pending the
Interrupt
interrupt).
clearedA.
interrupts,
cleared
ILAT A.level
as
unless aswell
unless
and
the
well
aretheas those
interrupt
as those
interrupt
not affected
being
service
being
service
by
presently
routine
presently
the routine
system-
serviced.
clears
chain the
at the
serviced.
clears the mechanism
ILAT that
level andthat
mechanism generated
aregenerated
not affected Interrupt
by theA,
Interrupt or
orifif
system-
A,
levelthe interrupt
process registers (SIC_IWR, SIC_ISR, SIC_IMASK,
level the processof
interrupt ofservicing
registers
servicing thetheinterrupt
(SIC_IWR, SIC_ISR,
interrupt clears
clears this
thisbit.
SIC_IMASK, bit.
SIC_IARx).
SIC_IARx).

09/23/21 Veton Këpuska 44

Interrupt Service Routine
 ISR address is stored in the Event Vector Table
 Used as the next fetch address when the event
occurs
 Program Counter (PC) address is saved to a register
 RETI, RETX, RETN, RETE, based on event
 Always concludes with “Return” Instruction
 RTI, RTX, RTN, RTE (respectively)
 When executed, PC is loaded with address stored in
RETI, RETX, RETN, or RETE to continue app code
 Optional nesting of higher-priority interrupts possible
 See app. note EE-192, which covers writing interrupt
routines in C (http://www.analog.com/ee-notes)

09/23/21 Veton Këpuska 45

Blackfin Peripherals
Blackfin Peripherals & Power
Management
 Common Peripherals (All Blackfins)
 SPI, UART, SPORT, WD, RTC
 PPI

 BF534/BF536/BF537 Peripherals
 TWI, CAN (Controller Area Network)

 BF536/BF537 Peripheral
 Ethernet

 DMA and Handshake DMA

 Power Manager

09/23/21 Veton Këpuska 47

Serial Communication Peripherals
 SPI (Serial Peripheral Interface)
 High-Speed SPI port (up to SCLK/4, max 33.25
MHz)
 Master/Slave compatible with control of up to 7
slave-selects
 Single-Duplex DMA (Either TX or RX)
 Typically used to interface with
 serial EPROMS,
 CPUs,
 converters, and
 displays
09/23/21 Veton Këpuska 48
Serial Communication Peripherals
 UART (Universal Asynchronous
Receiver/Transmitter)
 PC-style UART port (baud rate up to SCLK/16,
max 8.3125 MHz)
 Supports half-duplex IrDA SIR (9.6/115.2 Kbps
rate)
 Autobaud detection support through the use of
the Timers
 Separate TX and RX DMA support
 Typically used for
 maintenance port or
 interfacing with slow serial peripherals
09/23/21 Veton Këpuska 49
Serial Communication Peripherals
 SPORTs (Synchronous Serial Ports)
 High Speed Serial Port (up to SCLK/2, max 66.5 MHz)
 Variable word length support (3 - 32 bits)
 I2S-Compatible
 Separate TX and RX DMA support
 128 Channels out of 1024-Channel Window for TDM
support
 Primary and Secondary Data channels
 Typically used for interfacing with
 CODECs and
 TDM data streams

09/23/21 Veton Këpuska 50

Real-Time Clock Features
 Used to implement real-time watch or “life counter”
 Time of day, alarm, stopwatch count-down, and elapsed time since
last system reset
 Uses four counters - Seconds, Minutes, Hours, Days
 Equipped with two alarm features
 Daily and Day-And-Time
 Uses dedicated 32.768 kHz crystal to RTXI / RTXO
 Can be pre-scaled to 1 Hz to count in real-time seconds
 Uses dedicated power supply pins
 Independent of any reset
 Can take processor out of all low-power states

09/23/21 Veton Këpuska 51

Parallel Peripheral Interface - PPI
 Parallel Peripheral Interface
 Programmable bus width (from 8 – 16 bits in 1-bit steps)
 Bidirectional (half-duplex) parallel interface
 Synchronous Interface
 Interface is driven by an external clock (“PPI_CLK”)
 Up to 66MHz rate (SCLK/2)
 Asynchronous to SCLK
 Includes three frame syncs to control the interface timing
 Applications
 Driving LCD Interface
 General Purpose Interface to outside world
 High speed data converters
 Video CODECs

09/23/21 Veton Këpuska 52

Two Wire Interface - TWI
 Fully compliant to the Philips I2C bus protocol
 See Philips I2C Bus Specification version 2.1
 7-bit addressing
 100 Kb/s (normal mode) and 400Kb/s (fast mode) data rates
 General call address support

 Supports Master and Slave operation

 Separate receive and transmit FIFOs

 SCCB (Serial Camera Control Bus) support

 Only in Master mode
 Slave mode cannot be used because the TWI controller
always issues an Acknowledge in slave mode

09/23/21 Veton Këpuska 53

Controller Area Network (CAN)
 Adheres fully to CAN V2.0B standard
 Supports both standard (11-bit) and extended (29-bit) Identifiers
 Data Rates up to 1Mbit/second

 32 Configurable Mailboxes
 8 dedicated transmitters and 8 dedicated receivers
 16 configurable (transmit or receive)

 Dedicated Acceptance Mask for each Mailbox

 Data Filtering (first two bytes) can be used for Acceptance Filtering

 CAN wakeup from Hibernation (lowest static power consumption)

Mode

 CAN Protocol Stacks

 Automotive: CAN drivers and protocol stacks through Vector CANtech
 Industrial: Leading third parties will provide a full Industrial suite for CANOpen,
DeviceNet, etc.

09/23/21 Veton Këpuska 54

Ethernet MAC Features
 ADSP-BF536/537 Ethernet MAC has advanced features beyond IEEE
802.3:
 For improved performance:
 Automatic Checksum Computation for IP Header and Payload on RX Frames
 Programmable RX Data Alignment Mode for 32-bit Alignment
 Independent RX & TX DMA Channels with Delivery of Frame Status to Memory
 System Wakeup on Magic Packet for 4 User-Definable Wakeup Frame Filters

 For lower overall system cost:

 No PHY XTAL required – Buffered XTAL output from processor feeds PHY
 Connection to either MII or RMII PHY

 ADSP-BF536/537 enhances throughput and dataflow via these

features:
 Enhanced DMA channels allow for processor core independence
 Direction Control to exploit SDRAM physics
 Four SDRAM rows can be ‘open’ at any given time

 ADSP-BF536/537 overall networking bandwidth:

 Full 100Mbps wire speed on 1400-bit payload with an optimized networking stack
 UDP : ~44% processor core loading
 TCP/IP: ~75% processor core loading

09/23/21 Veton Këpuska 55

Blackfin Memory
 Blackfin Memory Overview
25MHz No need for second
Enet
XTAL XTAL PHY
25MHz Enet Data SDRAM

131MHz
1:64X PLL VCO
DMA
64 bit L1
Programmable Instruction
frequency and Large enough to run Max Bandwidth
application code 266MB/sec
voltage control
Cache available if
525 MHz operations from SDRAM
are desired
Rows are “open” in
Ext 4 SDRAM banks
32 Bus 16 reduces
page activation
L1 W/direction
Blackfin Data A Control
Makes
Processor best use
of
SDRAM
2 core fetches
or 1 fetch and 1
store

09/23/21 Veton Këpuska 57

Blacfin Memory Hierarchy
 As processor speeds increase (300Mhz – 1 GHz), it
becomes increasingly difficult to have large memories
running at full speed.
 The BF5xx uses a memory hierarchy with a primary goal
of achieving memory performance similar to that of the
fastest memory (i.e. L1) with an overall cost close to
that of the least expensive memory (i.e. L2)
L2 Memory
External
On-Chip Larger capacity
Higher latency
L1 Memory
CORE
Internal L3 Memory
(Registers) Smallest capacity
Single cycle access External
Largest capacity
Highest latency

09/23/21 Veton Këpuska 58

 Basics of Blackfin Memory
Architecture

Core >600MHz

16Kbyte
Single cycle to 16Kbyte
access L1 Instruction L1 Data Memory L1 Data Memory
Memory >600MHz
10s of Kbytes

Several cycles to DMA Unified L2 >300MHz

access
On-chip
100s of Kbytes
Off-chip
Several system cycles to access External
External
Unified Memory
Memory
L3
External Memory <133MHz
100s of Mbytes External Memory

09/23/21 Veton Këpuska 59

Configuration of Memory
 Best system performance can be achieved
when executing code or fetching data out of L1
memory
 Two methods can be used to fill L1 memory –
Caching and Dynamic Downloading – Blackfin
Processor supports both
 General Purpose processors have typically used the caching
method, as they often have large programs residing in
external memory and determinism is not as important.
 DSPs have typically used dynamic downloading, as they
need direct control over which code runs in the fastest
memory.
 Blackfin processors allow the programmer to
choose one or both methods to optimize
system performance.

09/23/21 Veton Këpuska 60

Address Registers
 One set of 32-bit general-purpose
Pointer registers
 P0-P5 (Pointer/Address registers),
 SP (Stack Pointer Register) and
 FP (Frame Pointer Register)
 One set of 32-bit DSP buffer
addressing registers
 I0-I3 (Index Registers),
 B0-B3 (Base Registers),
 L0-L3 (Length Registers), and
 M0-M3 (Modify Registers)
 All addresses are byte addresses into a
4 GB address space
09/23/21 Veton Këpuska 61
Address Registers

31 0
P0
Address P1

Registers P2
P3
SP points to supervisor stack in
P4
Supervisor mode and user stack in
P5
User mode
FP
SP
USP is accessible in supervisor
USP mode only – Allows access to user
31 0 31 0 31 0 31 stack location while in Supervisor
I0 L0 B0 M0 mode
I1 L1 B1 M1
I2 L2 B2 M2
I3 L3 B3 M3

09/23/21 Veton Këpuska 62

Addressing Modes
 Register Indirect Addressing
 Index Registers I0-I3 (32-bit and 16-bit accesses)
 Pointer Registers P0 – P5 (32-bit, 16-bit, and 8-bit accesses)
 Stack and Frame Pointer Registers SP, FP (32-bit accesses)

 Types of address pointer modify

 Modify/Post-Modify
 Linear addressing
 Circular buffering / modulo addressing
 Enables automatic maintenance of pointers to stay
within bounds of a circular buffer
 Bit-Reversal (Modify only)
 Pre-Modify with update (using Stack Pointer)
 Pre-Modify without update

09/23/21 Veton Këpuska 63

Linear vs. Circular Buffering
 Linear Buffer Access
 Index (I0:3) registers hold the address sent out on the address bus.
 Length (L0:3) register set to 0, thus disabling circular buffering.
 Default for C compiler
 Provisions in compiler to allow circular buffers
 Modify (M0:3) registers contain the value (positive or negative) that
is added to the I registers at the end of each memory access.

 Circular Buffer Access

 Base (B0:3) registers contain the circular buffer’s start address.
 Length (L0:3) register set to length of circular buffer.
 Modify (M0:3) value must be less than or equal to the length of the
circular buffer.
 Indexing wraps back to Base address when Index modification
exceeds Base + Length

09/23/21 Veton Këpuska 64

Circular Buffering Example
Address
0 0x00000001 1st Access 0x00000001

0x00000002 0x00000002 4th Access

4
8 0x00000003 0x00000003

C 0x00000004 0x00000004

10 0x00000005 2nd Access 0x00000005

0x00000006 0x00000006 5th Access

14
18 0x00000007 0x00000007

1C 0x00000008 0x00000008

20 0x00000009 3rd Access 0x00000009

24 0x0000000A 0x0000000A

28 0x0000000B 0x0000000B

 Base Address and Starting Index Address (B0 = 0; I0 = 0;)

 Buffer Length is 44 (L0 = 44;)
 There are 11 data elements and each data element is 4 bytes
 Modify Value is 16 (M0 = 16;)
 4 elements * 4 bytes/element

09/23/21 Veton Këpuska 65

Summary
 Basic Features of BF533 Processor
were introduced
 Comprehensive discussion of each
Processor feature related to audio
processing will be discussed in depth
in this class.

09/23/21 Veton Këpuska 66