DataSheeT

Time Delay Digital Beamforming

Example Design

DESCRIPTION FEATURES
Radar system has been using a hybrid of analog · Efficient DSP time delay algorithm
and digital beamforming (DBF). Sub-arrays of · BF engine time-shared between Tx and Rx
phase shifters are digitized at the sub-array output. · Arbitrary fine beam angle resolution – 0.02
Such system suffers from limited bandwidth and degree implemented
produces only one beam at a time. Fully DBF · Fully parameterizable design
solves both problems. Frequency domain DBF is
· 6-8 beams of 32 antenna in a Stratix V
very efficient in resource, but inherently
· Also completed with chirp generator, target
narrowband.
range emulation, Rx noise emulation, and
Time Delay BF (TDBF), on the other hand is natively pulse compression
wideband and allows scalable number of · Demo hardware controlled in Matlab
simultaneous beams. With the advance of high environment
density and low power FPGA, TDBF becomes
· Performance and Resource usage of a beam of
possible. This reference design used a very
32 antennas:
efficient and precise fractional delay algorithm to
achieve sub picosecond time delay. As a result,
Performance Spec. Spec. Spec. Spec.
beamforming at a very fine angle can be achieved.
Examples #1 #2 #3 #4
Sample Rate (MHz) 300 300 267 250
The design is implemented in Simulink with Altera Signal Bandwidth (MHz) 200 200 200 200
DSP Builder Advanced Blockset. To test the design Filter Length 6 8 12 16
in hardware, other supportive components like Expected SNR (dB) 34 52 60 65
chirp generator, target range emulation, Rx noise Multipliers (18x18) 416 544 800 1056
Logics (max 260k) 8140 8800 9300 10k
emulation, aperture tapering, and pulse
Block RAM 64 64 64 64
compression are also implemented. Compiled Fmax. (MHz) 310 304 284 284

Reference: C. Cheung, R. Shah, M. Parker, “Time APPLICATIONS

Delay Digital Beamforming for Wideband Pulsed
· Active Electronically Scanned Array (AESA)
Radar Implementation”, in IEEE International
Symposium on Phased Array Systems & · Radar, Sonar
Technology, p.448-455, October 2013 · Electronic Warfare and Software Defined Radio
5 Receive Digital · Phased Array Radio Telescope
Beamforming
Target
Emulation 4 DBF
Signal Processor Data Processor
Signal
Summation Pre- Fusion,
Noise Processing
DBF detect Compensation,
Emulation
Decisions
3 DBF Beam
Beam
Pulse
Compression 6
Forming
Weights
DBF Network Acceleration &
Doppler
Processing (MTI)
Bridging
...
Digital · Control
Waveform STAP · Power
DBF
Generator · Display
Target Detection
System Control · Communications
(CFAR)
2 1
For more information about Intel® FPGA Example Design Contact Intel
© Intel Corporation. Intel, the Intel logo, the Intel Inside mark and logo, Arria, Cyclone, Enpirion, Experience What’s Inside, Intel Atom, Intel Core, Intel
Xeon, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. See
Trademarks on intel.com for full list of Intel trademarks. *Other marks and brands may be claimed as the property of others.

April 29, 2020 Rev B