Scaling of MOS circuits

• Objectives
Scaling - Introduction
• What is Scaling?
• Proportional adjustment of the dimensions of
an electronic device while maintaining the
electrical properties of the device
10
10
6
( )
Feature S izem

1.5
1
1 0.8
0.6
0.35
0.25
0.18
0.13
0.09
0.1

1965 1970 1975 1980 1985 1990 1995 2000 2005

Year
Contd…
• VLSI technology is constantly evolving towards
smaller line widths and feature size.
• Reduced feature size generally leads to
– Better / faster performance
– More gate / chip
• More accurate description of modern
technology is ULSI (ultra large scale
integration.
 Properties of IC effected by Scaling
• Impact of scaling is characterized in terms of
several indicators or Figures of merit:
 Minimum feature size
 Number of gates on one chip
 Power dissipation
 Maximum operational frequency
 Die size
 Production cost
Full Scaling
 Scaling Models

1) Full Scaling (Constant Electrical Field)

• Ideal model – dimensions and voltage scale together by
the same scale factor.

2) Constant Voltage Scaling

• Most common model until recently – only the
dimensions scale, voltages remain constant

3) General Scaling
• Most realistic for today’s situation – voltages and
dimensions scale with different factors
Scaled nMOS Transistor
 Scaling Factors for Device Parameters

• Inorder to accommodate the three models,

two scaling factors 1/α and 1/β are used.

1/ β : scaling factor for supply voltage VDD and

gate oxide thickness D
1/α: linear dimensions both horizontal and
vertical dimensions
Scaling factors for Device Parameters
• Gate area Ag:

Where L: Channel length and W: Channel width

and both are scaled by 1/α

• Thus Ag is scaled up by 1/α2

• Gate capacitance per unit area Co or Cox :

Where εox is permittivity of gate oxide(thin-ox)= εins εo

and D is the gate oxide thickness scaled by 1/ β

• Thus Cox is scaled up by

• Gate capacitance Cg:

Thus Cg is scaled up by β * 1/α2 = β/α2

• Parasitic capacitance Cx:
• Cx is proportional to Ax/d
where d is the depletion width around source or
drain and scaled by 1/ α
Ax is the area of the depletion region around source
or drain, scaled by (1/α2 ).
• Thus Cx is scaled up by
• Carrier density in channel Qon :

• where Qon is the average charge per unit area

in the channel in the ‘on’ state.
• Co is scaled by β and Vgs is scaled by 1/β

• Thus Qon is scaled by 1

• Channel Resistance Ron :

• Where μ = channel carrier mobility and

assumed constant

• Thus Ron is scaled by 1

• Gate delay Td :

• Td is proportional to Ron*Cg

• Td is scaled by
• Maximum operating frequency fo :

• fo is inversely proportional to delay Td and is

scaled by
• Saturation current Idss :

• Both Vgs and Vt are scaled by (1/β). Therefore,

Idss is scaled by
• Current density, J:
J=Idss/A
• where A is cross sectional area of the channel
in the “on” state which is scaled by (1/ α 2)
• So, J is scaled by
• Switching energy per gate Eg:

• So Eg is scaled by
• Power dissipation per gate Pg:

• Pg comprises of two components: static component Pgs and

dynamic component Pgd:
• Where, the static power component is given by:

• And the dynamic component by:

Since VDD scales by (1/ β) and Ron scales by 1, Pgs scales by (1/
β2).
Since Eg scales by (1/ α2β ) and fo by (α2 / β), Pgd also scales by
(1/ β2).
Therefore, Pg scales by (1/ β2).
• Power dissipation per unit area Pa:
Power – speed product PT :
Summery of Scaling effects
 Two sets of goals by scaling:

1) Increased Transistor current-for faster charging and discharging parasitic capacitances

which increases the switching speed of the device which in turn increases the speed
of the entire circuit. This requires a short channel and high gate oxide field because
the inversion layer charge density is proportional to the oxide field.

2) Reduced Size-for density. This requires a short channel length and smaller channel
width, i.e., increase current per unit of the channel width so that the necessary
current can be provided.
 Two sets of constraints (Limitations) by scaling:
1) Acceptable leakage current when the transistor OFF. Even at gate voltage of 0 V
current flows and it is termed as sub threshold leakage current. This leakage
current is a constraint as if it exceeds a certain value may turn the transistor ON
which leads to malicious operation of the device. Actually the device is OFF but it
switches ON and gives wrong logic output voltage which may be fed to another
device and affects the entire circuit’s output voltage.

2) Acceptable reliability life time of the device and failure rate. Device reliability
depends on the oxide reliability. Lower the quality of the gate oxide the more it
allows leakage current through it and device fails. When scaling continues and
oxide becomes nanometer order thickness, silicon dioxide may not be suitable as
gate oxide and various alternatives like High-k gate materials are proposed. Hence
till now we understood these goals and constraints in the fabrication point of view.
In short the main issues are high performance (speed), high integration level (small
chip) and relatively low power are main design issues for VLSI circuits.