VLSI DESIGN

EE 401
WEEK 11 & 12

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DESIGNING HIGH SPEED CMOS
LOGIC NETWORKS

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• THE OUTPUT SWITCHING TIMES FOR THE FOLLOWING
CMOS LOGIC GATE IS GIVEN BY THE EQUATIONS:

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• GATE DELAYS CAN BE PREDICTED BASED
UPON THE PARAMETERS GIVEN IN THE
PREVIOUS EQUATIONS. CL IS THE LOAD
CAPACITANCE

• VLSI DESIGNERS HAVE TO DESIGN THE

CIRCUIT IN SUCH A MANNER THAT IT
PROVIDES PROPAGATION DELAY WITHIN
THE DESIRED LIMITS

• A STRUCTURED/FORMULATED APPROACH
IS REQUIRED FOR ESTIMATING THE GATE
DELAYS
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• LETS START WORKING WITH A UNIT FET AS
SHOWN BELOW:

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• IN CALCULATING THE DELAYS, THE MOST IMPORTANT
PARAMETER IS THE CAPACITANCE

• VARIOUS GATE CAPACITANCES FOR THE UNIT FET CAN

BE APPROXIMATED BY THE FOLLOWING EQUATIONS:

• IN DEVELOPING THE METHODOLOGY FOR

APPROXIMATING THE GATE DELAYS WE WILL FURTHER
ASSUME THAT ALL TRANSISTOR SIZES USED IN THE
DESIGN ARE A INTEGRAL MULTIPLE OF THE UNIT FET!

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FOR SUCH A CASE WE HAVE:

AND ALSO:

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THE DRAIN AND SOURCE CAPACITANCES OF THE
SCALED FET CAN BE APPROXIMATED BY:

COMBINING THE ABOVE WE REACH TO A VERY

IMPORTANT CONCLUSION OF THE SCALING
THEORY:

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SUPPOSE AN INVERTER IS BEING DESIGNED
USING THE MINIMUM SIZED FETs. OBVIOUSLY
THIS SHALL BE THE CASE OF ELECTRICAL
NON-SYMMETRY (WHY?)

THE RISE AND FALL TIMES FOR THE UNIT

INVERTER SHALL DIFFER! AND THESE SHALL
BE:

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HERE r IS THE MOBILITY RATIO OF THE nFET
TO THE pFET

THE INPUT CAPACITANCE OF THE UNIT

INVERTER IS:

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IF THE SAME UNIT INVERTER IS SCALED 3 TIMES
THEN OBSERVE THAT THE NO LOAD TIMINGS
WILL REMAIN ALMOST THE SAME AND THE
NEW TIMING EQUATIONS CAN BE WRITTEN AS:

THE INPUT CAPACITANCE OF THIS GATE SHALL

BE:

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CONSIDER NOW THE NAND2 GATE AS SHOWN
BELOW:

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COMPARED TO THE INVERTER NOW THERE ARE
THREE FETs THAT TOUCH THE OUTPUT NODE.
THUS A FACTOR 3/2 WILL BE MULTIPLIED WITH
THE INTERNAL CAPACITANCE.

SINCE THE pFETs ARE IN PARALLEL, THEIR

RESISTANCES SHALL REMAIN THE SAME AS
THAT OF THE INVERTER BUT AS THE nFETs ARE
IN SERIES THEIR RESISTANCES SHALL
BE DOUBLED! THIS WOULD THUS INCREASE
BOTH tf0 AND αnu BY A FACTOR 2. THE
EQUATIONS FOR NAND2 CAN THUS BE WRITTEN
AS:
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THE INPUT CAPACITANCE WILL BE THE MINIMUM
AND IT WILL BE GIVEN BY:

WHEN THE UNIT NAND2 IS SCALED THREE TIMES

AS SHOWN IN THE PREVIOUS FIGURE, THE
RESISTANCE PART OF THE EQUATIONS WILL
CHANGE AND IT WILL BE DIVIDED BY A FACTOR
OF 3 14
THE INPUT CAPACITANCE IS THUS:

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GENERALIZING WE CAN SAY THAT IF THE
NUMBER OF INPUTS IS ‘N’ AND THE SCALING
FACTOR IS ‘m’, TIMING FOR THE NAND N GATE
CAN BE APPROXIMATED BY:

AND OBVIOUSLY:

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FOR THE NOR 2 GATE AS SHOWN BELOW:

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THE TIMING EQUATIONS CAN BE APPROXIMATED
BY:

OBSERVE THAT HERE ONLY THE RISE AND FALL

TIMES HAVE BEEN REVERSED AS THE pFETs ARE
NOW IN SERIES AND THE nFETs ARE IN
PARALLEL!

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FOR THE 3 TIMES SCALED NOR2 GATE WE
HAVE:

AND FOR THE GENERALIZED CASE:

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THESE EQUATIONS CLEARLY DEPICT THAT
SWITCHING SPEED DEPENDS UPON:

1)NUMBER OF INPUTS (FAN IN)

2)TRANSISTOR SCALING FACTOR ‘m’

THE INPUT CAPACITANCE IS IMPORTANT

BECAUSE IT’S A MEASURE OF THE GATE’S
LOADING!

FROM THE ABOVE DISCUSSION WE CONCLUDE

THAT FOR A LOGIC CHAIN OF ‘M’ STAGES, WE
CAN APPROXIMATE THE DELAY BY SUMMING
THE DELAYS OF THE INDIVIDUAL STAGES! 20
 THUS:

HE INDIVIDUAL CONTRIBUTIONS TO THE TOTAL

ELAY WILL DEPEND UPON:
GATE TYPE
ITS SIZE
TYPE AND SIZE OF THE NEXT STAGE

WE MUST TAKE INTO ACCOUNT THE DIFFERENCE

ETWEEN THE RISE AND FALL TIMES ALSO! 21
 CONSIDERATION OF THE
RISE AND FALL TIME
IN CALCULATING THE TOTAL
CHAIN DELAY!

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 CONSIDER THE FOLLOWING CASCADED CHAIN
CIRCUIT:

NOTE VARIOUS TRANSITIONS CLEARLY. IT IS

IMPORTANT IN THE ANALYSIS!

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THE TOTAL DELAY CAN BE GIVEN BY THE
SUMMATION OF THE INDIVIDUAL DELAYS UNDER
SPECIFIC TRANSITIONAL CONDITIONS AS
FOLLOWS:

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APPLYING THE APPROPRIATE EQUATIONS
(AS PER THE TRANSITIONAL DELAYS) AS
FOLLOWS:

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THE TOTAL CHAIN DELAY CAN BE SIMPLIFIED
BY THE FOLLOWING:

OBVIOUSLY THE EXPRESSION FOR td WILL CHANGE

IF DIFFERENT TRANSITIONAL CONDITIONS WOULD
BE APPLIED!

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 THE ANALYSIS HAVE BEEN PERFORMED USING
THE MINIMUM SIZED FETS BUT IT CAN BE EASILY
EXTENDED TO A SYMMETRICAL DESIGN. FOR
THIS CASE βn=βp AND THE RISE AND FALL TIMES
SHALL BE EQUAL. WE GET:

THIS IS TRUE FOR A CIRCUIT WITH Wn=Wmin and

Wp=rWmin

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 THE INPUT CAPACITANCE THUS INCREASED
TO:

THIS NOW BECOMES A REFERENCE VALUE.

SCALING THE TRANSISTORS IN THE NOT GATE BY
‘m’ GIVES:

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 CONCLUSIONS
• IF ‘m’ IS USED TO SCALE BOTH pFETs and nFETs
EQUALLY, THEN THE RISE AND FALL TIMES
SHALL BE DIFFERENT FOR ALL THE GATES IN
WHICH N>1
• EQUALIZATION IN SWITCHING TIMES CAN BE
ACHIEVED ONLY WHEN BOTH THE FETs ARE OF
DIFFERENT SIZES
• IF PARALLEL CONNECTED FETs ARE SCALED BY
A FACTOR ‘m’ THEN SERIAL CONNECTED FETS
MUST BE INCREASED IN SIZE BY A FACTOR ‘mN’
TO OBTAIN A SYMMETRICAL DESIGN!

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