PCI Express Hard IP Quick

Start Guide with SOPC Builder

© 2009 Altera Corporation—Confidential

Objectives
 Implement a PCI Express system from design to
working model in under 45 minutes using an
Arria® II GX* device & SOPC Builder

 You will see

 How easy it is to create PCI Express designs using Arria II GX
device Hard IP blocks and transceivers
 How SOPC Builder simplifies complex systems like PCI Express

* Procedures presented may be similarly performed on Stratix IV GX devices

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 PCI Express Hard IP Quick
Start Guide with SOPC Builder
Altera PCI Express Solutions

© 2009 Altera Corporation—Confidential

Altera PCI Express Solutions
 Arria II GX FPGAs
 Arria II GX embedded transceivers
 Arria II GX PCIe Hard IP blocks
 SOPC Builder
 PCI Express Compiler

© 2009 Altera Corporation—Confidential

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Introducing Arria II GX FPGAs
 Increased system integration on a low-cost FPGA
 Up to 256k equivalent logic elements
 Up to 8.5Mbits of on-chip RAM and 736 18x18 multipliers
 Up to 16 full-duplex transceivers up to 3.75Gbps

 Lower power
 40nm process with 0.9V core voltage
 <100mW per transceiver channel (@ 3.125Gbps)

 Transceiver FPGA design made easy

 Built-in PCI Express hard IP
 Single design environment
 Protocol IP packs, design examples, and reference designs

Low Power, Low Cost, Easy to Use

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Arria II GX FPGA Architecture

DSP
• 56 to 736 multipliers
Logic
• 16K to 256K LEs Configurable I/O
• Up to 612 I/O
• 1-Gbps LVDS
Transceivers • 600-Mbps DDR2
• Up to 3.75 Gbps and DDR3
• 4 to 16 channels
• 100 mW per channel Internal memory
• 0.7 to 9 Mbits of
block memory
Hard PCI Express IP
• Up to 5 Mbits of
• Gen1.1 x1, x4, x8
LAB memory

Up to 6 PLLs

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 Transceiver Block Architecture
 Easily configured using Quartus® II
MegaWizard® plug-ins

Transceiver Channel 3

TX3 & RX3

Transceiver Channel 2

PIPE to FPGA
TX2 & RX2
PCIe Link

Central Control
Clock Management
Unit 1
Arria II GX device with
Unit (CCU)
Clock Management 8 transceiver
Unit 0

Transceiver Channel 1
channels (2
transceiver blocks)
TX1 & RX1

Transceiver Channel 0

TX0 & RX0

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PCI Express Hard IP Block
 Performs transaction, data link, and PHYMAC layer functionality
 Supports
 PCI Express Gen 1.1
 x1, x4 & x8 lane configurations
 Root port and endpoint applications
 Connects directly to embedded transceivers using internal PIPE interface
 Shared by two adjacent transceiver blocks
 Enabled through the PCI Express Compiler Wizard
Arria II GX FPGA
PCI Express Hard IP Block

Embedded Transceiver
Block
PIPE Transceiver Block n
Transaction Data Link PHYMAC
Transceiver Block 2
Layer Layer Layer
Transceiver Block 1 To / from
Transceiver Block 0 Slot or cable

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 PCI Express Hard IP Diagram
 Configurable maximum
payload size
PLD Fabric  128, 256, or 512 bytes
Transceiver Block PCI Express Hard IP Block
Clock & Reset Selection
 1 Virtual Channel
 4-Kbyte receive buffer
PMA PCS  2-Kbyte transmit retry
TL buffer

FPGA Interface
PCI Express Interface  64-bit application datapath
PIPE

Adapter
Application
Transceiver Block Protocol Stack Layer width
 Interrupt support (legacy,
Local Mgmt MSI & MSI-X)
IF
PMA PCS (LMI)  Advanced error reporting
Retry VC RX (AER) support
Buffer Buffer
 Power management
support
 Local management
interface (LMI) to access
configuration registers
 Status & debug interface

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Example PCIe Hard IP Location

GXBL2 Arria II GX Device with 12 channels

Channel3 & 1 hard IP block
Channel2
Channel1
Channel0
PCIe Hard IP
Block
GXBL1 (Slave)

PCIe Lane 7 Channel3

PCIe Lane 6 Channel2
PCIe Lane 5 Channel1
PCIe Lane 4 Channel0

GXBL0 (Master)
PCIe
PCIe Lane 3 Channel3
PCIe Lane 2 Channel2
PCIe Lane 1 Channel1
PCIe Lane 0 Channel0

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SOPC Builder
 System design tool enabling designers to describe their
system in design blocks
 Automates IP Block connectivity
 Supports both Memory-mapped and Streaming systems

Reduce Development Time by Weeks!

© 2009 Altera Corporation—Confidential
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PCI Express Compiler
 Configures PCIe
MegaCore® IP
function
 Includes all PCIe Hard
IP settings
 Includes embedded
transceiver blocks
 Output files
 Verilog HDL or VHDL
wrapper files
 Tcl constraint file
 SDC file for TimeQuest
timing analysis
 Application layer design
example & testbench to
verify chosen settings
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PCI Express / SOPC Builder Design Flow

2. PCI Express Compiler gets called

from SOPC Builder to configure
PCIe MegaCore block and add to
embedded system

1. Open SOPC Builder

from the Quartus II
software to build
embedded system

3. SOPC Builder
generates HDL that is
added to Quartus II
project for compilation
into Arria II GX device
© 2009 Altera Corporation—Confidential
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 PCI Express Hard IP Quick
Start Guide with SOPC Builder
PCI Express Endpoint using SOPC
Builder Demonstration

© 2009 Altera Corporation—Confidential

Example PCIe-SOPC Builder System

Memory DMADMA DMA

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PCIe Endpoint Design Example

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Design Example Simulation
 Modelsim™ simulation directory generated at
<sopc_builder_system>_sim
 Scripts to simplify setting up & running ModelSim
 Testbench files located in directory
<pcie_component_name>_examples
 Uses an auto-generated bus functional model (BFM) to emulate
the other end of the PCIe link
 Performs link initialization and generates verification messages
 Modify files altpcietb_bfm_driver.v or .vhd to perform additional
transactions

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PCI Express Compiler / SOPC Builder
Demonstration

Click here if demo does not open

 PCI Express Hard IP Quick
Start Guide with SOPC Builder
Summary

© 2009 Altera Corporation—Confidential

Summary
 SOPC Builder makes designing complex PCI
Express systems straightforward and simple
 Arria II GX Hard IP block provides a low-cost and
easy-to-use way to implement your PCI Express
solution

© 2009 Altera Corporation—Confidential

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
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Additional Materials
 Arria II GX FPGA Overview
 Arria II GX Getting Started
 Arria II GX Design Resources
 Altera PCI Express Solutions webpage
 Altera PCI Express Hard IP webpage
 Altera Online training
 PCI Express online training for Altera 40 nm devices
 Using SOPC Builder
 Altera Documentation
 Arria II GX Device Handbook
 PCI Express Compiler User Guide
 PCI Express protocol resources
 Download PCIe Specification at PCI-SIG (www.pcisig.com)
 Training and reference materials available from Mindshare Inc. (
www.mindshare.com)

© 2009 Altera Corporation—Confidential

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
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Your Feedback is important
 For any feedback or questions regarding this
training, please send an e-mail to
certfae@altera.com

© 2009 Altera Corporation—Confidential

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
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