ARM Cortex Processors (v7)

 ARM Cortex-A family (v7-A):

 Applications processors for full OS
 and 3rd party applications

 ARM Cortex-R family (v7-R):

 Embedded processors for real-time
 signal processing, control applications

 ARM Cortex-M family (v7-M):

 Microcontroller-oriented processors
 for MCU and SoC applications
Cortex family
Cortex-A8
 Architecture v7A
 MMU
 AXI
 VFP & NEON support
Cortex-R4
 Architecture v7R
 MPU (optional)
 AXI
 Dual Issue
Cortex-M3
 Architecture v7M
 MPU (optional)
 AHB Lite & APB
Cortex-M3 Processor

•RISC general purpose 32-bit microprocessor, released 2006

•Cortex-M3 differs from previous generations of ARM processors by
defining a number of key peripherals as part of the core:
–interrupt controller
–system timer
–debug and trace hardware (including external interfaces)
•This enables for real-time operating systems and hardware
development tools such as debugger interfaces be common across the
family of processors
•Various Cortex-M3 based microcontroller families differ significantly in
terms of hardware peripherals and memory
Cortex-M3 Processor Applications
Greater performance efficiency: more work to be done without increasing the
frequency or power requirements
–Implements the new Thumb-2 instruction set architecture
•70% more efficient per MHz than an ARM7TDMI-S processor executing Thumb
instructions
•35% more efficient than the ARM7TDMI-S processor executing ARM
instructions for Dhrystone benchmark
•Low power consumption: longer battery life, especially critical in portable
products including wireless networking applications
•Improved code density: code fits in even the smallest memory footprints
•Core pipeline has 3 stages
–Instruction Fetch
–Instruction Decode
–Instruction Execute
Automotive industry: allowing it to be used in real-time systems
Data communications: Bluetooth and ZigBee
Industrial control: the Cortex-M3 processor’s interrupt feature, low
interrupt latency, and enhanced fault-handling features make it a
strong candidate in this area.
Harvard architecture: it uses separate interfaces to fetch
instructions (Inst) and (Data)
•Processor is not memory starved: it permits accessing data and
instruction memories simultaneously
•From CM3 perspective, everything looks like memory
–Only differentiates between instruction fetches and data
accesses
•Interface between CM3 and manufacturer specific hardware is
through three memory buses:
–ICode, DCode, and System (for peripherals), which are defined to
access different regions of memory
Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set
Thumb-2 Instruction Set
•Thumb-2 instruction set is a superset of the previous 16-bit Thumb instruction set
•Provides
–A large set of 16-bit instructions, enabling 2 instructions per memory fetch
–A small set of 32-bit instructions to support more complex operations
The Cortex-M3 processor features:
• A low gate count processor core, with low latency interrupt processing that has:
— A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual.
— Banked Stack Pointer (SP).
— Hardware divide instructions, SDIV and UDIV.(Signed and unsigned Divide instructions)
— Handler and Thread modes.
— Thumb and Debug states.
— Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low
interrupt latency.
— Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit.
— Support for ARMv6 big-endian byte-invariant or little-endian accesses.
— Support for ARMv6 unaligned accesses.
• Nested Vectored Interrupt Controller (NVIC)
closely integrated with the processor core to achieve low latency interrupt processing.
Features include:
• Nested interrupt support
• Vectored interrupt support-When an interrupt is accepted, the starting address of the interrupt service
routine (ISR) is located from a vector table in memory
• Dynamic priority changes support-Priority levels of interrupts can be changed by software during run time.
• Reduction of interrupt latency- automatic saving and restoring , handling late arrival interrupts.
• Interrupt masking
— Priority grouping. This enables selection of pre-empting interrupt levels and non pre-empting interrupt levels.
— Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
— Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.
— Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.

• Memory Protection Unit (MPU). An optional MPU for memory protection, including:
— Eight memory regions.
— Sub Region Disable (SRD), enabling efficient use of memory regions.
— The ability to enable a background region that implements the default memory map attributes.
• Bus interfaces:
1.Code memory buses 2.System bus 3. Private peripheral bus
— Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interfaces.
— Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface.
— Bit-band support that includes atomic bit-band write and read operations.
— Memory access alignment.
— Write buffer for buffering of write data.
— Exclusive access transfers for multiprocessor systems.

• Low-cost debug solution that features:

— Debug access to all memory and registers in the system, including access to memory mapped devices, access to
internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is
asserted.
— Serial Wire Debug Port (SW-DP) or Serial Wire JTAG(Joint Test Action Group) Debug Port (SWJ-DP) debug
access, or both.
— Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
— Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system
profiling.
— Optional Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
— Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire
Output (SWO) mode.
— Optional Embedded Trace Macrocell (ETM) for instruction trace.
Bus interfaces
The processor contains four external Advanced High-performance Bus (AHB)-Lite bus interfaces:

ICode memory interface

Instruction fetches from Code memory space, 0x00000000 to 0x1FFFFFFF, are performed over this
32-bit AHB-Lite bus.
The Debugger cannot access this interface. All fetches are word-wide. The number of
instructions fetched per word depends on the code running and the alignment of the code in
memory.
DCode memory interface
Data and debug accesses to Code memory space, 0x00000000 to 0x1FFFFFFF, are performed over
this 32-bit AHB-Lite bus. Core data accesses have a higher priority than debug accesses on this
bus. This means that debug accesses are waited until core accesses have completed when there
are simultaneous core and debug access to this bus.
Control logic in this interface converts unaligned data and debug accesses into two or three
aligned accesses, depending on the size and alignment of the unaligned access. This stalls any
subsequent data or debug access until the unaligned access has completed.
Note
ARM strongly recommends that any external arbitration between the ICode and DCode AHB
bus interfaces ensures that DCode has a higher priority than ICode
System interface
Instruction fetches, and data and debug accesses, to address ranges 0x20000000 to 0xDFFFFFFF and
0xE0100000 to 0xFFFFFFFF are performed over this 32-bit AHB-Lite bus.

For simultaneous accesses to this bus, the arbitration order in decreasing priority is:
• data accesses
• instruction and vector fetches
• debug.
The system bus interface contains control logic to handle unaligned accesses, FPB remapped
accesses, bit-band accesses, and pipelined instruction fetches.

Private Peripheral Bus (PPB)

Data and debug accesses to external PPB space, 0xE0040000 to 0xE00FFFFF, are performed over
this 32-bit Advanced Peripheral Bus (APB) bus. The Trace Port Interface Unit (TPIU) and
vendor specific peripherals are on this bus.
Core data accesses have higher priority than debug accesses, so debug accesses are waited until core accesses
have completed when there are simultaneous core and debug access to this bus.
Only the address bits necessary to decode the External PPB space are supported on this
interface.
ETM interface
The ETM interface enables simple connection of an ETM to the processor. It provides a channel
for instruction trace to the ETM. See the ARM Embedded Trace Macrocell Architecture Specification.

AHB Trace Macrocell interface

The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB trace macrocell to the processor. It
provides a channel for the data trace to the HTM.
Your implementation must include this interface to use the HTM interface. You must set TRCENA to 1 in the Debug
Exception and Monitor Control Register (DEMCR) before you enable the HTM to enable the HTM port to supply trace
data.
Stack Pointer R13
R13 is the stack pointer. In the Cortex-M3 processor, there are two stack pointers. This duality
allows two separate stack memories to be set up. When using the register name R13, you
can only access the current stack pointer; the other one is inaccessible unless you use special
instructions MSR and MRS. The two stack pointers are:

• Main Stack Pointer (MSP), or SP_main in ARM documentation: This is the default
stack pointer; it is used by the OS kernel, exception handlers, and all application codes
that require privileged access.

• Process Stack Pointer (PSP), or SP_process in ARM documentation: Used by the

base-level application code (when not running an exception handler).

R14: The Link Register

When a subroutine is called, the return address is stored in the link register.

R15: The Program Counter

The program counter is the current program address. This register can be written to control the
program flow.
Link Register R14
R14 is the link register (LR). Inside an assembly program, you can write it as either R14 or
LR. LR is used to store the return program counter when a subroutine or function is called—
for example, when you’re using the BL (branch and link) instruction:

main ; Main program

…
BL function1 ; Call function1 using Branch with Link
; instruction.
; PC function1 and
; LR the next instruction in main
…
function1
… ; Program code for function 1
BX LR ; Return
Some of the memory locations are allocated for private peripherals such as
debugging components. They are located in the private peripheral memory region.
These debugging components include:

• Fetch Patch and BreakPoint Unit (FPB)

• Data WatchPoint and Trace Unit (DWT)
• Instrumentation Trace Macrocell (ITM)
• Embedded Trace Macrocell (ETM)
• Trace Port Interface Unit (TPIU)
• ROM Table
The last 0.5 GB of memory is for the system-level components, internal peripheral buses,
external peripheral bus, and vendor-specific system peripherals. There are two segments
of the private peripheral bus:

• AHB private peripheral bus, for Cortex-M3 internal AHB peripherals only: This includes
NVIC, FPB, DWT, and ITM.

• APB private peripheral bus, for Cortex-M3 internal APB devices as well as external
peripherals (external to the Cortex-M3 processor): The Cortex-M3 allows chip
vendors to add additional on-chip APB peripherals on this APB private peripheral bus
via an APB interface.
shown in the memory map is merely a template;
individual semiconductor vendors will provide detailed memory maps
including the actual location and size of ROM,RAM, and peripheral
memory locations.
 Memory Access Attributes

The memory attributes you can find in the Cortex-M3 processor include
these:

• Bufferable- write to memory carried out by write buffer

• Cacheable- Data from memory can be copied to a memory cache(speed

up the program execution)

• Executable- can fetch and execute program

• Sharable- Data can be shared by multiple bus masters

Code memory region (0x00000000–0x1FFFFFFF): This region is executable, and the cache attribute is
WT (Write Through). You can put data memory in this region as well.

• SRAM memory region (0x20000000–0x3FFFFFFF): This region is intended for

on-chip RAM. Write is buffered, and the cache attribute is WB-WA (Write Back, Write Allocated). This
region is executable, so you can copy program code here and execute it.

• Peripheral region (0x40000000–0x5FFFFFFF): This region is intended for peripherals. The accesses
are non cacheable. You cannot execute instruction code in this region (Execute Never, or XN in ARM
documentation).

• External RAM region (0x60000000–0x7FFFFFFF): This region is intended for either on-chip or off-
chip memory. The accesses are cacheable (WB-WA), and you can execute code in this region.
External RAM region (0x80000000–0x9FFFFFFF): This region is intended for either on-chip or off-chip
memory. The accesses are cacheable (WT), and you can execute code in this region.

• External devices (0xA0000000–0xBFFFFFFF): This region is intended for external devices and/or
shared memory that needs ordering/nonbuffered accesses. It is also a non-executable region.

• External devices (0xC0000000–0xDFFFFFFF): This region is intended for external devices and/or
shared memory that needs ordering/nonbuffered accesses. It is also a nonexecutable region.

• System region (0xE0000000–0xFFFFFFFF): This region is for private peripherals and vendor-specific
devices. It is non-executable.
For the private peripheral bus memory range, the accesses are strongly ordered (noncacheable,
nonbufferable).
For the vendor-specific memory region, the accesses are bufferable and noncacheable.
 Default Memory Access Permissions

The Cortex-M3 memory map has a default configuration for memory access
permissions. This prevents user programs from accessing system control memory
spaces such as the NVIC.

The default memory access permission is used when either:

• No MPU is present
• MPU is present but disabled
CMSIS – Cortex Microcontroller Software Interface Standard