Professional Documents
Culture Documents
Moor’s Law
Modeling
Validations
Implementation
Embedded System Design Flow
1- Specification
DSP Code
Chip)
FPGA(Field Programmable
Gate Array)
ASIC (Application –Specific _ Integrated - Circuit)
Full-Custom
High Low
Volume
ASIC Hardware Embedded System
Bad:
◦ Very expensive ($5-$75M/design)
◦ Very High Risk (Several total failure points)
FPGA Filed Programmable Gate Arrays
Revenues ($)
Time (months)
Design Issues
Complex Systems!
◦ How to get it working?
(on time, on budget)
Need for abstraction and design reuse
◦ How to test it?
Real Time Physical Embedding
◦ Does it meet constraints?
◦ Design Budgeting: Power, Size, Cost, Reliability
◦ What are the exploitable design options?
VII-Examples of embedded system
Moors Law