RD1

2018-06-15

EE Solutions
Eliot

翊傑科技股份有限公司
 Database Planning
Database
 PC Database type
Whole schematic/simulation database to tar.gz
Datasheet / Schematic document
 Workstation Schematic
Converted IC5 new IP library(with unified AnalogRoot) to IC6
Spectre can’t run ....
 IP Database
To updated IP properties & features for new added IP
=> classified one version to sales, Rory’s IP database confirmed ok
=> got Mars phy schematic and tidied ok

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 Project Support
ERI001
 2017/8/4 meeting minutes
R108 (5V power in)
 DAC / LDO pin alignment => DAC could use clock confirmed ok
 One version DRC/LVS pass => comp output, IO, OSC loading &
VCD functional pattern checked
 Datasheet updated I2C register usage / Updated testing items
 Reviewed PCB layout and replied to Riko

R108a (10V power in)

 Address need to separate for R108 & R108a
 DAC / LDO pin alignment => DAC use I2C clock
 One version DRC/LVS pass => VCD functional pattern checked
 Datasheet updated I2C register usage / Updated testing items
 Reviewed PCB layout and replied to Riko

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 Project Support
ERI001 / ERI002
 Goodman Status
 1/11 Sent R108A top & HIB for post-sim & layout review => replied R108A postsim ok
 ERI002 analog w/ IO post-sim done => got report for DCC

 EES Status
 Doing analog simulation w/o all analog connected ok => to tide netlist to KJ
 to build up DCC tar files done and wait for QFN16 socket

IP Name R108 R108A Functional Schematic APR Frame Final Frame Note Post-sim

POR_3.3V 　 　 2017/11/10 2017/11/15 2017/12/20 2017/12/18 Done Ok

IO 　 　 2017/11/15 2017/12/8 2017/12/20 2017/12/18 Done -

LDO 5V to
　 x 2017/12/8 2017/12/14 2017/12/20 2018/1/25 Done Ok
3.3V
Comparator 　 x 2017/12/8 2017/12/13 2017/12/20 2018/1/25 Done Ok

OSC 20MHz 　 x 2017/12/8 2017/12/14 2017/12/20 2018/1/25 Done Ok

PGA /
　 x 2017/12/8 2017/12/13 2017/12/20 2018/1/25 Done Ok
DACx4
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 Project Support
ERI001
 Measuring
 I2C : read / write ok, need to tie high reset pin to ensure work
 OSC : functional ok for all 4 bits => 3 samples similar to simulation results
 LED Driver : output waveform ok => ratio is correct
 Comparator : output abnormal but input is PGA & DAC
 test chip measure functional ok for 0.1 – VDD-0.1
 Leakage : around 70mA seems to high & EMMI hot spot found
 LDO : functional ok but rising fail for some boards, need very short time
 Checked simulation 1s still can’t see this effect
 test chip some also measured this result
 PGA : output has noise 1.1MHz & 7.3MHz same w/ Riko
 DACx4 : test chip ok
 test mode DC level & ramp fail ERI001 Debug
List
 discussing add VREF / IBIAS internally and to send file to Goodman
 found EMMI hot spot

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 Project Support
ERI002
 Measuring
 DACO_V : test mode ramp out functional ok
 CX measured ripple in DACO_V
 Goodman said it need external C to compensate
 System : Riko is measuring output voltage & current

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 Project Support
ERI002 – Riko (OP+ADC+DAC)
 12/15 meeting minutes
 Riko
 提供 MUC, OP datasheet
 提供更新版本的電路圖、 waveform 以及其 min. / max. / step 等資訊
 提供 DAC mapping table
 量測 OP 第一級的輸出訊號圖形
 EES
 整理 MCU, OP 相關的 input loading
 根據選定製程做 OP simulation 確認頻寬 ( 時程會比較長，需要選定製程拿到 spice
model 後才可進行 )
 Package 會被封膠包住，需注意散熱問題，先找 QFN 試算 IC 溫度

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 Project Support
SA – Riko (R110 Single Chip)
 R110 request
studying now .... looks similar to R109
updated spec. and sent (11/2)
still target 3.3V & 30-40V BCD process
go w/ CM to visit Riko and to fix spec. (11/28) => table ok
but need to add waveform
Spec. fixed (11/28) sent to review that need to specify
driving & added protection diodes => need to update .....
Updated excel spec. on 12/25
Mentioned external POR R 240K will burn out IC but 100K
does not => VP mentioned pending now .....

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 Project Support
EZX018 – RTC
 RTC Current too high (>1mA)
POR_VDT stable, ISO1233, V1233VD no leakage
1.2V on/off still has current thus should no interface issue
DAC/CODEC power / ground / signal resistance too high
to degrade the waveform
SDC syntax error skipped a lot of cells has no H2L LS
DDR SIP issue found DLL do not get power source
sent DDR SIP review report to SAM
QIR finished and go Jeilin for discussion
ESD HBM/MM all passed checked do need to change IO

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 Project Support
EZX018
 IO
Need to arrange power / ground location based on IP
Sent RDL layer to Sam for preview again => modify RDL

 IP
DAC/ADC, CODEC main power / ground layout drawn
Need to check all metal width & resistance in floorplan =>
checking now

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 Project Support
EPW010&011
 System
Tell Oh that virtual ground is not possible to do on EES
Ground 200mV => Oh to check ground bypass C & meter
connections

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 Project Support
EPW010&011
 PPA
Help making one version to do RDL routing flow trial
Will update IO for virtual ground insertion that still need to
update PPA
Updated RDL trial PPA and sent out
PLL power can’t off thus could only control PWR_CUT_N
to power down PLL
 STD
Help check Endcap / FillbiasNW usage
SLVT do not have VNW / VPW pins can’t pass LVS

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 Project Support
EPW015
 IO
IO type sent to Mr. Oh
Analog company asked to tie 3 ground cells internally
Isolated CorePSUB Core IO
Vo ltage 0V / 5V 0V 0V / 1.8V 0V / 1.8V 0V / 5V OUT 0V / 5V IN
Pad Type VDDCI PUSB VDDC VDDI / GNDI VDDO / GNDO VDDR / GNDR
VDDCIPADP v
VDDPADP v v
VDDCAPDP v
VDDOPADP v
VDDRPADP v
VDDORPADP v v
GNDCIPADP v
GNDPADP v v
GNDOPADP v
GNDRPADP v
GNDORPADP v v
PSUBPADP v

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 Project Support
SA – J-Metric
 Carrier 800KHz / message could reduce to 100Hz
 Design will need 5V to 32V
 Focus on HV switch & input amplifier stage for MPW
 100p loading switching current too high to drive
 Checked Johnny BCD not suitable for analog switch
 Functional N DMOS simulation is ok but Vbs=0
 VIS replied substrate is in dependent but Viso_d=0
 To find out new LCD process w/ 32V

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 Project Support
SA – UBEC
 3.3V to 1.8V low quiescent LDO requested
 discussed 5uA Iq and driving for 20mA
 Right now checking .... BGP 3uA

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 Project Support
SA – empia
 0.11um shrink flow document sent to Kenny
 Explain to Kenny flow & operation that spice need to
re-run and notice the post-sim RC netlist
 MIPI 0.11um / 0.13um need to compare waveform
MIPI got design database that need account
 DLL designed by Johnny and help support
xxx

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 Project Support
ENL001
 STD
Help check layout contact -usage
Spice model ??

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 Project Support
ESC011 – Syncomm
 VDT
worked in 0.153um, suggest not to use this one as POR

TT, -40C, BJT_SS

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 Project Support
ESC011 – Syncomm
 VDT
Modified Vt point 1.4-1.3V to 1.5–1.4V

Corner Hysteresis (mV)

TT 98.67
TTt0b0 98.92
TTT1b0 98.74
TTt0B1 97.86
TTT1B1 95.81
SS 98.85
FF 97.84
SF 97.87
FS 98.72

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 Project Support
ESC011 – Syncomm
 Flow
Need to go through the new command file for 0.153um
Use old one to scale 1.111x
Answered ESD question and remind of weak point
 IP
VDT Start-up circuitry keep the same just modify R ratio
POR got high leakage in FF 125 corner removed leakage
source & raise POR output from 0.2V to 1.0V in this case
POR to layout .... => 9/13
IO bond pad density > 3% from GSMC wavied
build up GSMC 0.18/0.162/0.153um IP & IO to DCC (3/8)

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 Project Support
ESC011 – Syncomm
 ESD fail
Pin to VSS / VCC18 / Pin fail
Pin to VSS need to check and asked fail chips to decap
got EAO002 ESD test report ok as well as PPA/Bonding
Decap chip do not see any burnt out
sent out EAO002 gds & bonding pad compare picture
sent out ESC011 B40, I40U, I40D & XOSE02 compare
wait for new package ESD test & to do FA for SIP IC

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 Project Support
EPW010&011
 PPA
checked SSO / power / ground / POC cells
assigned PLL power / ground types according to IP vendor
resistor value need to check after correct coordinators
sent EPW010 (VD) PPA to Mr. Oh (6/14)
sent EPW011 (H) PPA to Mr. Oh (6/25)
Updated PPA to Oh and reminded him of RF’s variated a
lot in bond pad numbers / sequence
Found leakage due to SLVT device library confirmed
To do floating gate simulation at TT corner done
IO POS simulation done and sent to Oh
To sim Pad floating input pad => 2.xxV
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 Project Support
EPW010&011
 Input PAD Floating Simulation
Pad 2.06 ~ 2.28V due to POC control function

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 Project Support
EPW010&011
 011 Floating Simulation
LPX can’t run but LPE ok. NAND2B & DFFSQ both 2
cells
All 36uA for LPE and LPX estimated 900uA for 25X

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 Project Support
SA – Riko (2 chips + New BCD)
 New request
10 – 30V low side / high side driver as additional chip
To write down all device list => sent slides to Ken (7/21)
 sent device list, got STD unit cell < 20um2 for 0.2um process
 asking key design rule to check DAC size

To draw N/P driver block diagram for Golden’s review

 Golden think 0.6mA ok based on present functional block
 get PDK and sent to Golden thus all documents sent

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 Project Support
EJT001
 Process & Layout
sent IO & other IP schematics to Felix
CX’s IP has done and ready to send to CX’s review
POR / OSC need to place in IO ring area
OSC asked to extract more detail netlist
LSHL / LSLH / DELAY Cell timing sim ok to make LIB
 IUMB reverse
start to reverse and IUMB reverse done (6/30)
created lib, LEF by removing PORE related items
start to redesign => functional checked ok
adding MIM on IO filler for 1.5V & 3.3V
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 Project Support
SA - Vishare
 300MHz LVTTL IO speed issue
Simulation 0.11um UMC IUMB IO for 300MHz
Reference showed 300MHz w/ 5pf load
CX replied FPGA output 300MHz ok and Steven
confirmed IO driving is 12mA
SMIC also has programmable IO from 3 – 20mA
Sent out TSMC 0.13um DLL 312.5MHz brief datasheet
Design remove DLL plan & will sent receiver IC datasheet
Sent UMC IO library name to HC (6/22)

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 Project Support
ETG001
 Testing
help double confirm the measured databased for fine
tuning new AC ranges
 ESD
Help arrange both 80 pins & 128 pins
passed 2KV / 200V test
continue to do latch-up test => passed to update report
 Spec.
Sent out spec. to HC

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 Project Support
SA – empia
 300MHz DLL w/ 32 phases, 3+2 DLL w/ 6mA
 EKR005
 200~400MHz DLL w/ 16 phases, 28mA
 32 phases need new design and different scheme to save power

 Master+Slave digital DLL architecture

 PFD & Delay line simulation
 datasheet preliminary (3/31) and sent to Min (4/6)
 PFD simulation and discussing w/ HD
 ask Kenny could update freq. from 150-300MHz
 updated datasheet to 150-300MHz and sent

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 Project Support
SA – empia DLL
 Library
SMIC 0.11um / 0.13um
STD Library for speed test => HC sent to empia
MVIO, SSTL18
SRAM
Via ROM
Zoe downloaded whole library
Kenny confirmed 0.13um STD workable
32K OSC customization need 3 bits of current
consumption option

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 Project Support
EPW010&011
 PPA
checked SSO
checked power / ground / POC cells
assigned PLL power / ground types according to IP
vendor
resistor value need to check after correct coordinators
sent EPW010 (VD) PPA to Mr. Oh (6/14)
sent EPW011 (H) PPA to Mr. Oh (6/25)
Updated PPA to Oh and reminded him of RF’s variated a
lot in bond pad numbers / sequence
sent die size to Oh

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 Project Support
SA – Riko (OP+ADC+DAC)
 Spec.
VP Wu sent one version of system schematic
RFQ updated 2A & B chip size (6/9)
 IP
OP
ADC 14bits for 0.0001 accuracy
To search 5V DAC / ADC IP first
OP is the key cause no specific input signal level
Try GF 0.18um 5V OP schematic & simulation (3/24)
Updated die size again w/ 2 chips solutions (3/27)
meeting w/ KEN and switched to 3.3V/13.5V process (6/7)
VIS 3.3V/13.5V don’t have MIM or PIP capacitor
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 Project Support
SA – Riko (OP+ADC+DAC)
 Question
could use I2C clock in start to correct internal oscillator**
System start time available 40~50ms (requested 10ms)
keep comparator output level w/o switching & latch type
set register to setting variable period range & driver ratio
System use MCU to polling signal and count certain cycles
for 1-3MHz, could count X cycles to pass output signal
Issue is to estimate error timing, keep 18~22us at present
Need to estimate 2 signal addition & subtraction (sim...)
Updated 1 Channel to 2 Channels PGA (need DACx4)
Germany could use QFP4x4 for one channel case
Updated 2 channels block diagram
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 Project Support
SA – Riko (OP+ADC+DAC)
 Measurement

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 Project Support
ESO003 – SRAM
 Frame (Now 3,650um x 478um)

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 Project Support
ESO003 – IO
 UMC EHV55 IO not available
EHV55 is 1.2 / 6 / 16V process that only has 6V under
drive 3.3V MOS
Contact Alex and they also got pure 1.2V IO cells
Need to design pure 1.2 IO cells and has asked Kevin to
get ESD layout ready (5/10)
PMOS : 25u x 20/0.1u NMOS : 20u x 20/0.1u
1.2V pure I/O circuitry ESD doc check & sim. => done
to come out IO, SRAM LEF (6/13) => done
sent IO schematic / netlist to Kevin (6/17)
IO layout finished

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 Project Support
SA – Syncomm
 IP
asked POR / LDO => EAO002 0.153um used
VDT 0.18um just pass 0153um simulation
 PLL
found internal SOP flow that need perl to convert length
found netlist / gds in 0.18um scale in layout backup dir
running 0.18um scale 0.9945 w/ 0.153um spec. PLL
16MHz input, 128MHz output TT,SS case ok (5/12)
Asking PLL spec. exceed 2X – 8X (FF/SS TR work)
 16 X (24/2 )= 192MHz   (for USB)
 12.288 x  (48/3) = 196.608MHz  (for 96K audio)
 7.5264 x (48/2) = 180.633MHz (for 44.1K audio)
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 Project Support
SA – Vishare – IO 300MHz sim

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