Lecture 4: Gate Level

Minimization and DLD Software

CS-216: Digital Logic Design

September 13, 2015
 Lecture Overview

• Gate level minimization through K-Maps

• Examples
• Logic Friday Software Installation
• Altera Quartus II Software Installation
 Karnaugh Maps

• Gate level minimization through Boolean

Algebra is rather time-consuming.
• Karnaugh Maps, or K-Maps: Visual technique
to find out minimal Boolean expression from a
truth table.
• Up to 5 variables. Six max, but difficult. Not
possible for more than six input variables.
 Don’t Care Conditions

• A combination of inputs which is either illegal, and

never allowed to occur OR a combination which even
if it occurs, is inconsequential for the problem being
considered.
• Don’t care condition, denoted in truth table by an X.
INPUT OUTPUT
a b q
0 0 X
0 1 0
1 0 1
1 1 X
 Constructing K-Maps
Rules:
• Two variable K-Map i. Represent as sum of
• Truth table: products form (not
canonical)

INPUT OUTPUT ii. Separate 1’s in the table

in Groups of 2n: ..1, 2, 4,
a b q 8, …
0 0 0
0 1 0 iii. One group of 1’s forms
one product.
1 0 1
1 1 1 iv. Take uncomplemented
form for 1, complemented
form for 0.

v. Drop variables for which

values changes.
 Constructing K-Maps (continued)
NOTE:
• Three variable K-Map Only one bit changes at one time.

• Truth table:
 Constructing K-Maps (continued)
• Four variable K-Map
• Truth table:
a b c d q
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
a b c d e q
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 1
0 0 0 1 1 1
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 1
1 0 0 1 0 1
1 0 0 1 1 1
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 0
1 1 1 0 0 1
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 1 1
Constructing K-Maps (continued)
 Prime Implicant

• A prime implicant is a product term obtained

by combining the maximum possible number
of adjacent squares in the map.
• If a minterm in a square is covered by only one
prime implicant, that prime implicant is said to
be essential.
• The final expression should have all essential
prime implicants.
 Computer Algorithms
• Quine-McCluskey algorithm:
– Based on prime-implements, uses technique similar to K-maps.
– Deterministic
– Easy to implement, but complexity and memory requirements increase
exponentially with number of variables.
• The method involves two steps:
– Finding all prime implicants of the function.
– Use those prime implicants in a prime implicant chart to find the essential
prime implicants of the function, as well as other prime implicants that are
necessary to cover the function.

• Esresso algorithm.
• The final expression should have all essential prime implicants.
 Computer Algorithms

• Quine-McCluskey algorithm:
– Based on prime-implements, uses technique similar to K-maps
– Deterministic
– Easy to implement, but complexity and memory requirements
increase exponentially with number of variables.
– The method involves two steps:
• Finding all prime implicants of the function.
• Use those prime implicants in a prime implicant chart to find the
essential prime implicants of the function, as well as other prime
implicants that are necessary to cover the function.
 Computer Algorithms (continued)

• Espresso algorithm:
– Developed at UC Berkley/ IBM.
– Based on combination of classical algorithms and
and heuristics
– Very efficient
– Logic Friday
• Free software: Windows front-end for
– Espresso Algorithm
– misII (component in Berkley’s OctTools)
Logic Friday Software Application Installation

1. Download (www.sontrak.com, or get from Mr. Razzaq, who has

already downloaded it).
2. Install (run lf114_setup.exe). You may get a security warning,
depending upon computer setup.
3. If you decide to proceed, you’ll get an installation window. Press
on Next>
Logic Friday Software Application Installation

4. Accept the agreement:

Logic Friday Software Application Installation

5. Chose installation directory (will require 2.8MB of free space):

Logic Friday Software Application Installation

6. Chose installation directory (will require 2.8MB of free space):

Logic Friday Software Application Installation

7. Chose start menu location

8. Choose option to create desktop shortcuts and file association.
9. You’ll get a summary window. Choose Install option to proceed.
Launch the application at the end.
 Logic Friday

10. Launch the application at the end.

11. Choose File->New->Truth Table to enter Truth table
 Logic Friday

12. Double-click on output column to choose 0, 1 or X.

 Logic Friday

13. Choose Truthtable->submit. You’ve now successfully entered the

table.

14. Explore different operations from the operations menu, e.g.

minimize, generate C code etc. Try out different option from the
menu.
 Quartus II (Altera VHDL Development Environment)

• Altera: One of the two largest vendors of PLD’s (FPGA/CPLD)

• Quartus II Software (v14.x onwards do not support 32-bit
operating systems; we will use v13.1)
• EPM240 CPLD design kit and USB Blaster programmer
 Quartus II Installation
• Of the three files provided, run QuartusSetupWeb-13.1.0.162.exe. Do not
run ModelSimSetup file. It will be installed automatically.
• You can download it yourself (free edition), but it takes a very long time.
Ask Mr. Razzaq for the files which he’s already downloaded.
 Quartus II Installation
• After the initial introductory spash screen, you’ll get the welcome dialog
box. Click on the Next button.
 Quartus II Installation
• On the license agreement, choose to accept it, and click on Next button.
 Quartus II Installation
• You will be provided with an option for the installation directory. Either
choose the path that you want Altera software to be installed in, or use
the default option and click on Next button.
 Quartus II Installation
• Next you’ll be given an option to choose the components that you need.
Select the ones shown here, and click on Next button. Other components
can be chosen later at any time.
 Quartus II Installation
• The installation directory, required space and available disk space will be
indicated. Click on the Next button.
 Quartus II Installation
• Installation will start. Most of the time will be taken up by unpacking the
files.
 Quartus II Installation
• Once the files are unpacked, actual installation will start. The first part of
the installation will be installing the ModelSim module, which will again
take a while since the files have to be unpacked. You don’t have to install
ModelSim separately.
 Quartus II Installation
• Once ModelSim files have been unpacked, it will install Verilog and VHDL
model files. You’ll have to be patient.
 Quartus II Installation
• Next, it will create uninstaller for ModelSim. All this takes time.
 Quartus II Installation
• After ModelSim has been installed, the rest of the installation will
proceed, and then an uninstaller will be created for Quartus software
itself.
 Quartus II Installation
• After the installation is complete, you’ll be prompted to have shortcuts
created on the desktop and to launch Quartus II software. Click on the
Next button.
 Quartus II Installation
• After the spashscreen is shown, you’ll be asked to enable sending Talkback
data to Altera. Choose the option to disable it, otherwise it will put load
on your network.
 Quartus II Installation
• Next, you’ll get a dialog box for different options. Choose to run Quartus II
software.
 Quartus II Software
• In the next screen (not shown here), choose not to upgrade the software.
We won’t need to do that for the duration of the class. The Quartus II
software main screen will now show up.
 Quartus II Software – Next Steps

• Next lecture will cover briefly:

– Installing device drivers for USB-Blaster (Programmer/
Debugger) that we will be using for programming.
– Sample LED project that you’ll compile and download on
the EMP240 CPLD kit. Different files constituting the
project will be explained.
– Brief introduction will be provided for the VHDL file, and
different parts will be explained.
 Summary

• Minimization of Boolean expressions (and

hence logic gates)
– Boolean Algebra
– K-maps
• Even if CAD software is available to do this, the
knowledge and practice in manual methods is
absolutely essential in order to design
optimally.