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CLOCK DOMAIN CROSSING

STATIC TIMING ANALYSIS (18MVE3E3)
NAME: USN:
Aishwarya K M 1RV20LVS01
Aman Shaikh 1RV20LVS02

Course Teacher: Dr. Shylashree N

Designation: Associate Professor
Department of Electronics and Communication Engineering

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Outline of the Presentation

Introduction
Literature Review
Clock Domain crossing
o Definition
o Issues
o Synchronizing techniques
Advantages, Disadvantages and Application
Conclusion
References

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Introduction
• Integrated circuits are becoming more complex day by day.

• A digital circuit that includes flipflops are generally related to clocks. For simpler case there are
usually one clock.

• The need for low power devices had lead to usage of asynchronous clock based design models.

• This concept is known as clock domain crossing.

• This usage of multiple clocks can create various problems in the design.

• To avoid this careful analysis of the timing paths and verification of design is required.

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Literature Survey
SL No. Title Author Published in Year Summary
1. Clock domain crossing — An 7th Mediterranean 2018 This paper describes the problem of clock
advanced course for future digital M. Bartik Conference on domain crossing for a multi clock based
design engineers. Embedded Computing digital design. It also discusses solutions for
(MEC) CDC in an FPGA.

2. Multi-clock domain synchronizers 2015 International 2015 This paper demonstrates how meta-stability
S. Hatture and Conference on occurs in CDC boundary. It also presented a
Computation of Power, comparison of basic synchronizers on the
S. Dhage Energy, Information basis of latency time to reduce the
and Communication propagation of meta-stability and to reduce
(ICCPEIC) the data loss in multi-clock design

3. Static analysis of asynchronous 2019 Design, 2019 This paper describes a methodical approach
clock domain crossings S. Chaturvedi Automation & Test in for static analysis of structural issues in
Europe Conference & asynchronous CDCs.
Exhibition (DATE)

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Literature Survey
SL No. Title Author Published in Year Summary
4. Conclusively verifying clock-
G. Plassan, H. -J.
2016 IFIP/IEEE 2016 They proposed a semi-automatic methodology
domain crossings in very large International to formally verify clock-domain
Peter, K. Morin-
hardware designs Conference on Very synchronization protocols in industrial-scale
Allory, F. Rahim,
Large Scale hardware designs. This method also verifies the
S. Sarwary and D.
Integration (VLSI- functional correctness.
Borrione
SoC.

5. Clock domain crossing formal 2020 IEEE 2020 This paper proposes a meta-model of
M. Kebaili, J.
verification: a meta-model. International High synchronizer that speeds up the proof and
Brignone and K.
Level Design ensures its better automation. In the process
Morin-Allory
Validation and Test they also discussed various synchronisers as
Workshop (HLDVT) well.

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Definition
• It is defined as the process of passing a signal or vector (multi bit signal) from one clock domain to
another clock domain.

• This may lead to timing errors like violation against recommended setup/hold time of a logic gate on
the boundary resulting in an error.

• If a clock with frequency 20MHz and a divide by 2 clock driven from 10MHz clock are treated
as a single clock domain design. However, designs which have two unrelated clocks (different
clock frequencies) or clocks from two different sources (even with same frequency) are treated as
multiple clock domain designs.
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Issues
1. METASTABILITY :- • If the transition on signal A happens very close to the
active edge of clock C2, it could lead to setup or hold
violation at the destination flop “FF2”.

• As a result, the output signal B may oscillate for an

indefinite amount of time. Thus the output is unstable
and may or may not settle down to some stable value
before the next clock edge of C2 arrives. This
phenomenon is known as metastability and the flop
“FF2” is said to have entered a metastable state.

• Apart from other consequences, it also increases the

propagation delay leading to timing issues.
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Issues
2. DATA LOSS :- • Whenever a new source data is generated, it may not
be captured by the destination domain in the very first
cycle of the destination clock.

• In the example shown, even though the input is

transitioning, it is not captured by the second clock.

• Also, the next transition in input is not captured in

second rising edge. Instead it gets captured only in the
These are generally avoided by using various next clock edge.
techniques like FIFO, handshake signals etc.
• All these can lead to data loss.

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Issues
•  Assume that “00” and “11” are two valid values for a
3. DATA INCOHERENCY :- signal X[0:1] generated by clock C1.
• There is a transition from 1->0 on both the bits of X.
Both the transitions get captured by clock C2 in the
first cycle itself. Hence the signal Y[0:1] becomes
“00”.Next, there is a transition from 0->1 on both the
bits of signal X.
• Here the rising edge of clock C2 comes close to the
transition on signal X. While the transition on X[0] is
captured in the first clock cycle, the transition on X[1]
gets captured in second clock cycle of C2.
• This results in an intermediate value of “10” on Y[0:1]
which is an invalid state. Data coherency is lost in this
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Synchronization of CDC Data Signals

I. Passing Data through MUX synchronizer
•
• In order to synchronize data, a control pulse is generated
in source clock domain when data is available at source
flop.

• Synchronized control pulse is used to sample the data on

the bus in destination domain.

• Data should be stable until it is sampled in destination

clock domain.

• Usually used when multiple data bits are present for

transmission.

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Synchronisation of CDC Data Signals

II. Handshaking between Clock domains • In this synchronization scheme request and acknowledge
mechanism is used to guarantee the sampling of correct data
into destination clock domain.

• This technique is mainly used to synchronize vector signal

which is not changing continuously or very frequently.

• The sender places a data onto data bus and then synchronizes
a “req” signal to the receiving clock domain. When the req
signal is recognized in the destination clock domain, the
receiver clocks the data into the register and then sends an
The disadvantage of using this method is the latency required to
“ack” signal through a synchronizer to the sender. When the
pass and recognize the handshaking signals for each data word. sender recognizes the ack signal, the sender changes the value
being driven on the data bus.

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Synchronisation of CDC Data Signals

III. Passing Data by FIFO between clock domains

• A dual port memory is used for the FIFO storage.

• One port of the FIFO is controlled by the sender, which puts

data into the memory as fast as one data word per write clock.

• The other port is controlled by receiver, which pulls data out

of the memory, one data per read clock.

• In some cases, there are extra signals used to indicate

whether the FIFO is full, empty or partially full.

• The figure shows a dual clock FIFO synchroniser.

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Comprehensive CDC verification solution

• Static analysis to identify synchronization error.
• Protocol assertion generation to ensure correct transfer of data.
• Reconvergence verification with metastability injection.

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CDC test planning process

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Advantages Disadvantages
 Allows the design to have multiple functional and test modes.  If clocks are not synced properly, it will lead to incorrect
functionality.
 Optimizes power usage
 Not properly covered by Validation.
 It helps to comply with multiple protocols.
 Needs to be carefully analyzed and verified.
 It plays a huge role in SoC integration . IP from many sources
can be linked.

Applications
 Used in multi clock based designs.

 Used in circuits where fast clocks are not required for the entire design.

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Conclusion
• In this seminar, we discussed about the concept of Clock Domain Crossing.

• The discussion included the definition of the CDC and some of the issues that is caused by these.

• We have also discussed about different synchronization methods used to overcome this.

• Later on, to give a broader perspective, the discussion was routed to industry verification method.

• Finally, we have discussed the advantages, disadvantages and the applications.

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References
1. M. Bartik, "Clock domain crossing — An advanced course for future digital design engineers," 2018 7th Mediterranean
Conference on Embedded Computing (MECO), 2018, pp. 1-5, doi: 10.1109/MECO.2018.8406004.
2. S. Hatture and S. Dhage, "Multi-clock domain synchronizers," 2015 International Conference on Computation of Power,
Energy, Information and Communication (ICCPEIC), 2015, pp. 0403-0408, doi: 10.1109/ICCPEIC.2015.7259493.
3. S. Chaturvedi, "Static analysis of asynchronous clock domain crossings," 2012 Design, Automation & Test in Europe
Conference & Exhibition (DATE), 2012, pp. 1122-1125, doi: 10.1109/DATE.2012.6176664.
4. G. Plassan, H. -J. Peter, K. Morin-Allory, F. Rahim, S. Sarwary and D. Borrione, "Conclusively verifying clock-domain
crossings in very large hardware designs," 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-
SoC), 2016, pp. 1-6, doi: 10.1109/VLSI-SoC.2016.7753555.
5. 2020 IEEE International High Level Design Validation and Test Workshop (HLDVT), 2020, pp. 136-141, doi:
10.1109/HLDVT.2016.7748267
6. Clifford E Cummings Synthesis and Scripting Techniques for Designing Multi Asynchronous Clock designs. SNUG 2001.
7. R. Ginosar, Fourteen ways to fool your synchronizer, Proceedings of IEEE Asynchronous circuits and Systems, 2003.
8. Ping Yeung, Five Steps to Quality CDC Verification, Mentor graphics white paper.
9. Chris Kwok and Roger Sabbagh, Comparison of Metastability Modeling Methods, Mentor Graphics White paper.

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THANK YOU …!

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