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A hybrid design approach of PVT tolerant, power efficient ring VCO

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DOI: 10.1016/j.asej.2019.10.009

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Electrical Engineering

A hybrid design approach of PVT tolerant, power efficient ring VCO

Madhusudan Maiti, Suraj Kumar Saw, Abir Jyoti Mondal, Alak Majumder ⇑
Integrated Circuits and Systems (i-CAS) Lab, Department of Electronics & Communication Engineering, National Institute of Technology, Arunachal Pradesh, Yupia,
District-Papumpare, Arunachal Pradesh 791112, India

a r t i c l e i n f o a b s t r a c t

Article history: This article unveils a new hybrid configuration of ring type VCO (voltage controlled oscillator) consisting
Received 28 July 2019 of CMOS and current starved inverter to generate full voltage swing. A certain number of such inverters
Revised 25 September 2019 are cascaded alternatively to obtain the output frequency (fosc). The novelty lies in the fact that this design
Accepted 20 October 2019
offers a good trade-off of power, frequency and gate count against CMOS based or current starved based
Available online xxxx
design counterpart. In a 90 nm process, the highest fosc achieved for a 7th stage VCO device footprint is
1.78 GHz with a power dissipation of 44.59 mW at a supply and control voltage of 1.2 V and 1 V respec-
Keywords:
tively. The simulated phase noise and output noise of the layout read to be
95.15dBc/Hz and
CMOS
Current starved

144.55 dB respectively measured at 1 MHz offset frequency along with the corresponding figure of
VCO merit (FOM) of
173.67dBc/Hz. In order to understand the robustness and scalability of the proposed
Low power design, the performances are observed using Monte Carlo study and as small as UMC 28 nm CMOS
Tuning range process.
Ó 2019 Ain Shams University. Production and hosting by Elsevier B.V. This is an open access article under
the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction
The VCO is treated as one of the vital building blocks in a com-
munication system such as wireline communication, SerDes cir-
cuit, clock & data recovery (CDR), phase locked loop (PLL) and
optical communication etc. One of the configurations is made of
ring oscillator [1], which is constructed using chain of the cascaded
delay cells structuring a loop. The most important benefits are
attaining better tuning range [2], tiny chip size and easy fabrication
process compared to LC oscillator. It finds wide use in communica-
tion systems [3] because of good frequency range, ease of imple-
mentation and compatibility with any sort of CMOS process. To
address the increasing demand for low power operation, wide tun-
ing range and large integration, a lot of works on CMOS voltage
controlled ring oscillator (VCRO) were carried out in literature,
where the frequency tuning capability is recognized by bias cur-
rent of each delay cell and this current is liberally controlled by
gate voltage. Moreover, the frequency tuning range (FTR) of ring
⇑ Corresponding author.
E-mail address: majumder.alak@gmail.com (A. Majumder).
Peer review under responsibility of Ain Shams University.
Production and hosting by Elsevier
oscillator (RO) is wide and a few available strategies for accom-
plishing it in ring VCO are changing the stack capacitor, managing
no. of stages and the driving ability. However, every method
adopted has its own inborn weaknesses such that in few prior arts
the frequency tuning is varied by the strength of positive feedback
and the manner in which input is applied [4,5]. As the latch power
consumption is not directly related to the control voltage; the fre-
quency tuning range (FTR) is not wide enough. Subsequently, in
spite of having wide FTR, the availability of low supply voltage in
the construction of the delay cell by stack of transistors is a con-
cern [6]. It is worth mentioning that changing the tuning range
as a function of load capacitor results in significant chip area. Fur-
ther, tuning range can also be modulated by alternating the delay
cells in subsequent stages. However, such modifications in delay
cell stages consume more power and chip area. Lastly, the
frequency-voltage characteristics of VCO have become nonlinear
if the driving capability is altered. The differential delay cell ring
oscillator circuit designed using altering driving capability is found
to have large power consumption, area and a tail current source. In
2018, Shirini et al. [7] presented a differential VCRO with wide fre-
quency range and higher frequency only to find penalty in terms of
phase noise and power consumption. This is solved by Kumar et al.
[8]; but offers low figure-of-merit. A power-area efficient current
starved VCO was proposed based on linearized current control
techniques by Saideh et al. [9] in 2019, which outputs low fre-
quency and poor tuning range. Therefore, the present study is
intended to design a ring VCO with a simple design structure to

https://doi.org/10.1016/j.asej.2019.10.009
2090-4479/Ó 2019 Ain Shams University. Production and hosting by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
2 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx
achieve wide tuning range, small layout area and low power
consumption.
The article is structured in the following manner: A brief note
background of RO along with prior research is discussed in Sec-
tion 2. Section 3 briefly states the function of new hybrid design
followed by the corresponding performance metrics and analysis
in Section 4. A detailed comparison with previous works is high-
lighted in Section 5. Section 6 describes the scalability of the design
at lower process. Finally, Section 7 concludes the work.
2. Background and prior arts
The ring oscillator (RO), formed as a cascaded delay cells is of
two types: single ended RO and differential RO. In both approaches,
the delay of each stage is controlled by control voltage (Vc), which
is shown in Fig. 1 [5,6].
The frequency of oscillation (f osc ) depends on the stage count
and is given by [5]:
1
f osc ¼
2ntdelay
where n is number of stage and t delay is delay time of each delay
stage. Also, the phase noise LðDf Þof the ring VCO [10,11] is
expressed as:
2
8 kbt T V dd f osc
LðDf Þ ¼
3g P V char Df 2
where V char ¼ DcV , DV = Gate overdrive voltage,kbt = Boltzmann con-
stant, T = Absolute temperature, c= a coefficient which depend on
the device condition. g = characteristics constant, Df = Offset fre-
quency and P = total power dissipation. Moreover, the FTR of ring
type VCO is expressed in [12]:
f high
f low
FTR ¼  100%
f high
Both the higher (f high ) and lower frequency (f low ) values depend
on the circuit supply (Vdd) and control voltage (Vcont).
From the numerous studies, it is noted that existing LC oscilla-
tor circuit suffers from certain loopholes. For example, LC tank
oscillator has huge fabrication complexity large chip area and poor
tuning range [13]. In order to overcome the same, CMOS RO was
demonstrated in [1] with more penalties in oscillation frequency.
In [13] and [14], a few techniques are addressed to oscillate at
lower frequency with moderate perfection. A few high frequency
and high figure of merit (FOM) ring oscillator designs were
attempted in [15,16] only to suffer from very short tuning range.
The article [17] highlights a circuit with ultra-wide tuning range
and reasonable phase noise performance; but that came at the cost
of high power consumption, which is taken care of a bit by [18]
with very poor phase noise. A few other works are reported in
[19,20] with high power consumption and low tuning range. In
order to get better tuning range, Rout et al. in 2014 [21], suggested
the use of current starved ring VCO with more number of repeated
transistor delay cells. This approach was comparatively easier; but
the oscillation frequency did not match up to the expectation. The
Fig. 1. Block of ring oscillator: (a) Single ended (b) Differential.
Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
design approach in [22,23] improved the oscillation frequency
after giving away penalty in terms of power consumption and tun-
ing range. In 2017, a high oscillation frequency with moderate
phase noise at the cost of comparatively very high power con-
sumption was presented in [24,25]. The work in [26] introduced
a VCO to oscillate at higher frequency at the cost of power, low tun-
ing range and FOM.
Taking into account the above pros and cons, it is attempted to
design a VCO having low power, wide tuning range, moderated
phase noise and low die area. In this attempt, CMOS and current
starved inverters are used at alternating stages to achieve wide
tuning range while controlling the charging or discharging current
of current starved circuit. In fact, the use of CMOS inverter in the
design increases the oscillation frequency and makes it more suit-
able for low power applications. It is observed that the mixed mode
design achieves a comparable oscillation frequency and a wide
tuning range at the expense of low power dissipation and smaller
chip area. In comparison to conventional design, the average power
is found to have decreased significantly along with gate counts.
ð1Þ
3. Description of the proposed VCO
A ring type 7-stage VCO is displayed in Fig. 2(a). To obtain sus-
tained and controlled oscillation, a requisite alterations are to be
entertained by each delay stage. In alternating stages, CMOS delay
ð2Þ cells (P2, N3; P5, N6; etc) are cascaded with current starved one (P3,
P4, N4, N5; P6, P7, N7, N8; etc) in order to generate the required fosc.
The control voltage (Vcont) applied at the gate of NMOS (N1) is used
to control the gate voltages of current starved gates, P3, N4 and so
on, thereby adjusting the charging and discharging current of delay
cells for the purpose of generating fosc. In fact, the delay is adjusted
by the gate voltages of the current starved gates. It is observed that
the fosc of the 7 stages ring VCO is inversely proportional with the
delay of the circuit.
ð3Þ
The physical device footprint of proposed VCO is designed using
90 nm CMOS 1P4M process file and is illustrated in Fig. 2(b), where
the silicon area happens to be as small as 0.000111 mm2 only. With
a Vdd of 1.2 V, the corresponding output and Vcont (when simu-
lated using Cadence Virtuoso) are plotted in Fig. 3 to undertsand
the manner in which fosc changes with subsequent variations in
Vcont. The oscillation is found to carry approx 50% duty cycle
(48.21% to be exact), which depends on the voltage at the gate of
current starved inverter section (P3, N4 and so on).
4. Analysis of performance metrics
The performance of the layout of proposed VCO is analysed for
90 nm CMOS technology on Cadence virtuoso environment. The
computation of these metrics at different corners along with
Monte Carlo run is performed on the new VCO designed using
the dimensions available in Table 1.
4.1. Noise analysis
Phase noise (PN) computation is important as it steers jitter for
not meeting a persistent clock period. The phase noise vs frequency
is plotted in Fig. 4 to indicate a small value of
95.15dBc/Hz at
1 MHz offset frequency. This value further decreases as the fre-
quency increases. The plot of output noise (ON) vs frequency is also
shown in Fig. 4. The corresponding value at 1 MHz offset reads to
be
144.54 dB. Table 2 summarizes the noise values at different
corners for both no skew and 5% skew and they are found to be
almost unchaged.
 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx 3

Fig. 2. Proposed voltage controlled oscillator (a) circuit and (b) layout @90 nm CMOS.

start oscillation after giving a step response in control signal. Also,

the oscillation frequency is computed at a supply and control sig-
nal of 1.2 V and 1 V respectively. It is observed that the alteration
of each metric with corner is quite small. Also, a tiny standard devi-
ation is detected for all parameters when simulated with 5% pro-
cess skew, thereby proving the robustness of the circuit.

4.3. Analysis of VCO gain

The tuning sensitivity of VCO (Gain) is defined as the ratio of

change in fOSC to that of Vcont and is written as [4]:

Df osc
K v co ¼ ð4Þ
DV cont
The gain plot (KVCO vs Vcont in Fig. 5) is found to have increased
linearly up to 0.5 V and subsequently saturated beyond 1 V. At
1.2 V supply, the corresponding value of KVCO is found to be
392.77 MHz/V at an oscillation frequency of 1.78 GHz.
Fig. 3. Transient analysis with control voltage.
4.4. Effect of control voltage sweep

Table 1 The variations in Pavg and fosc as a function of Vcont and Vdd is
VCO device dimensions.
shown in Fig. 6. Pavg is found to be almost constant beyond Vcont
Device Aspect Ratio (W/L) changing between 0.28 V and 0.8 V, when the controlling transis-
NMOS (nm) PMOS (nm) tors of current starved section change their region thereby offering
comparably higher resistance to output lower power dissipation.
N1 & N2 N3 to N12 P1 to P11
240/100 120/100 120/100 The tuning behaviour of a ring type VCO must be mostly linear
in nature. It is observed from Fig. 6 that for a Vcont ranging from
0.8 V to 1.4 V, the computed slope frequency (the VCO gain) is
almost constant for different Vdd. The slope of oscillation fre-
quency is found to be linear beyond 0.8 V thereby resulting in fre-
quency tuning range (FTR) between 16.1 MHz and 1.86 GHz.

4.5. Performance with temperature variation

For NN process file, the plot of fosc vs. junction temperature of

Fig. 4. PN & ON as a function of frequency.
4.2. Analysis of average power, delay, fOSC
The performance metrics such as power dissipation (Pavg), delay
and oscillation frequency (fOSC) of the proposed circuit are evalu-
ated at different corners for both ‘no skew’ and ‘5% process skew’
and summarizes in Table 3. It is worth mentioning that, in this case
the metric ‘delay’ corresponds to the response time of the VCO to
the die has been produced in Fig. 7 for a Vdd of 1.2 V. In this plot,
a variation of fosc by 0.575 GHz corresponds to a change in temper-
ature from 0 °C to 100 °C, thereby indicating a variation of
5.75 MHz in fosc for 1 °C change in temperature for Vdd = 1 V. For
the given variation in temperature Pavg is found to have changed
by 1.2 lW, which indicates a tiny alteration of 0.118 lW/oC only.
4.6. Monte Carlo analysis
The histogram in Fig. 8 involving the plot between sample size
and fosc & Pavg has been generated referring to the Monte Carlo
study [27,28] of NN process file. Following the histogram data,
the foscis noted to get shifted by less than a percent; however Pavg

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
4 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx

Table 2
Noise performance at different corners.

Pro-cess Cor-ners No skew 5% process Skew

PN (dBc /Hz) ON (dB) PN (dBc/Hz) ON (dB)
Mean Std Dev (m) Mean Std Dev (m)
NN
95.1
144.5
95.1 87.6
144.5 236.9
FF
93.5
144.0
93.5 89.9
144.0 251.5
FS
94.1
145.4
94.1 61.2
145.4 208.0
SF
94.6
144.2
94.6 77.5
144.2 251.1
SS
97.1
145.0
97.0 97.9
145.0 217.1

Table 3
Performance metrics of power, delay and oscillation frequency.

Process Corners No Skew 5% Process Skew

Pavg (mW) Delay (ps) fosc (GHz) Pavg (mW) Delay (ps) fosc (GHz)
Mean Std. Dev. Mean (ps) Std. Dev. Mean Std. Dev.
NN 44.59 29.46 1.78 44.58 0.266 29.48 0.391 1.78 0.034
FF 62.53 22.03 2.41 62.51 0.310 22.06 0.254 2.41 0.043
FS 41.38 32.63 1.71 41.39 0.074 32.74 0.277 1.71 0.037
SF 38.69 95.44 1.56 38.68 0.648 95.53 0.231 1.56 0.022
SS 27.89 43.84 1.18 27.87 0.222 43.98 0.661 1.18 0.024

Fig. 5. VCO gain vs. control voltage.

Fig. 8. Monte-Carlo Analysis of (a) PAVG (b) fOSC.

is found to be almost same to the enlisted no skew data of NN pro-

cess file of Table 3.

4.7. Figure of Merit

Fig. 6. Effect of control voltage on (a) PAVG (b) fOSC.

The commonly used figure of merit (FOM) of VCO is accounted
based on the phase noise, resonant frequency and power burned by
the circuit and is expressed using the following equation [29]:



f osc pav g
FoM ¼ LðDf Þ
20log þ 10log ð5Þ
Df 1mW

where LðDf Þ is phase noise at Df offset frequency and pav g is power

dissipation in mW. The same equation is taken into consideration
while analysing our hybrid VCO, which reads a FOM of

173.67dBc/Hz.

4.8. Best/worst case analysis

To observe best or worst possible behaviour of the design, the

circuit is simulated and analysed through FF corner (@1.26 V and
Fig. 7. Effect of temperature on (a) PAVG (b) fOSC.
40 °C) and SS corner (@1.14 V and 90 °C) respectively. The

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx 5

Table 4
Performance metrics @PVT variation.

Parameters NN @ 27 °C FF @
40 °C SS @ 90 °C
Average power (mW) 44.59 69.79 25.52
Osc. frequency (GHz) 1.78 3.21 0.877
PN (dBc/Hz) @1MHz
95.15
92.74
97.48
ON (dB) @1MHz
144.54
144.40
144.83
Tuning Frequency (GHz) 0.083–1.84 0.108–3.29 0.059–1.05
Tuning Range (%) 95.48 96.81 94.38

obtained result is summarized in Table 4. The noise components Fig. 10. (a) Single CS-inverter section (b) Small-signal model.
and tuning range are observed to be almost unaltered; whereas
Pavg and fOSC are noted to be changed by decent amount from best
corner (FF) to worst corner (SS). Again, the circuit is analysed by g m1
incorporating a noise voltage in power supply (such that noise is
V x1 ¼
ðV cont
V x2 Þ ð8Þ
g m0
±10% of supply voltage having 10 MHz variation) only to get a tiny
0.61% deviation in oscillation frequency, thereby claiming the cir- g m1
V x2 ¼ :V cont ð9Þ
cuit to be a sturdy one. What is important to note here is that, g m1 þ g m2
the hybrid CS-CMOS VCO is detected to be well functional even
After merging Eqs. (8) and (9), we get;
in worst case.


1 1
V x1 ¼ g m1 V cont
ð10Þ
4.9. Hybrid VCO vs current starved VCO: g m1 þ g m2 g m0
The ON resistance of NMOS transistor ‘N5’ðRON;5 Þ is mathemati-
To justify the worth of proposed hybrid CS-CMOS design
approach against the current starved based VCO, we have analysed cally expressed as:
both configurations for 90 nm CMOS at the supply and control sig- 1
RON;5 ¼ W    ð11Þ
nal of 1.2 V and 1 V respectively. The summary of performance ln :C ox : L 5
: V gs;5
V th;5
metrics may be observed from Fig. 9. The hybrid VCO is noted to
achieve an increase in fOSC by 82.66% after giving away a mere pen- 1
alty of 21.33% in terms of power consumption. Though the noise RON;5 ¼ W    ð12Þ
ln :C ox : L 5
: V x2
V c
V th;5
parameters are found to be almost constant, we have perceived
an advantage of 44.85%, 2.79%, 25.81% and 18.02% for KVCO, FoM, Considering, V c ¼ V in
V th6 and putting the value of V x2 in
gate count and FTR respectively. equation (12), we obtain;
The reason of obtaining wide FTR is explained with the follow-
1
ing setup shown in Fig. 10, which shows a small-signal model of RON;5 ¼ W  h i ð13Þ
current starved inverter section. ln :C ox : :
L 5 g
g m1
m1 þg m2
:V cont
V in þ ðV th;6
V th;5 Þ
Applying KCL at node x1 and x2, we get;
V x1 V x1
V x2

g m0 :V x1
¼ g m1 ðV cont
V x2 Þ þ ð6Þ
r ds0 r ds1

V x1
V x2 V x2
g m1 ðV cont
V x2 Þ þ ¼ g m2 :V x2 þ ð7Þ
r ds1 r ds2
Neglecting the effect of channel length modulation, both the
above equations may be re-arranged as;

Fig. 11. Transient of Test Setup incorporating 7-stage CS-CMOS inverter and 7-
Fig. 9. Comparison Conventional CS-VCO & new VCO. stage CS inverter at Vcont = 0.2 V.

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
6 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx

Table 5
Performance comparison with prior arts.

Parameters [30] IEICE [29] ISSCC [31] DTIS, [32] EESCO- [33] JSSC, [34] IJCA, [35] TCAS- [36] Micro-elec- [24] IEEE Ac- This
2019 2016 2015, IEEE, 2015, 2013 2011, I, 2011 tronics 2011, cess, 2017 work
Technology. (nm) 40 65 65 90 90 180 180 180 180 90
Supply (V) 1.1 1 1.2 1 0.6 3.3 1.8 1.8 1 1.2
Pavg (mW) 1.1 2.51 7.68 0.309 0.771 35.05 10 12.6 2.5 0.0446
Oscillation 1.38 3.47 3 0.450 0.480 0.369 1.055 1.92 1.03 1.78
Frequency (GHz)
Tuning Range (%) 37.68 68.5 61.53 – 94 99.9 4.27 18 0.53 95.48%
Phase Noise at
98.05
98.7
94
105.7
89.0
88
103.0
91
105.5
95.15
1 MHz (dBc/Hz) @771 MHz
FOM (dBc/Hz)
160.4
165.6
77
162.88 – – –
149.1 –
173.67
Area (mm2) 2800 3000 – 946 1900 – 2378 – 32,000 111.30
Structure Ring Ring Ring Ring Ring Ring Ring Ring Ring Ring

Table 6
Performance metrics in 28 nm technology.

Power Supply (V) Oscillation Frequency Range (GHz) Tuning Range (%) Circuit Parameters @ VCONT = 1 V
Pavg (mW) fosc(GHz) Phase Noise (dBc/Hz) @ 1 MHz Output Noise (dB) @ 1 MHz
1.0 0.0019–2.74 99.93 17.21 2.74
83.10
140.22
1.2 0.0028–5.04 99.94 38.81 3.81
82.01
138.44
1.4 0.0038–7.07 99.94 67.63 4.18
82.29
135.89

Similarly, the ON resistance of PMOS transistor (RON;4 ) is com-
puted to be written as;
1 aggressively lowers down the process nodes for chip design. These
RON;4 ¼ W    
lp :C ox : L 4
g m1 :V cont gm0
1

gm1 þg
1
m2

V in
ðV tp4 þ V tp3 Þ
Referring to Eqs. (13) and (14), the frequency tuning range (a
function of Vcont) may also be termed as a function of ON resis-
tance of controlling transistors of CS section. To understand the
modulation of RON4 and RON5, a test setup is carried out with
7-stage CS-CMOS inverter chain and 7-stage CS-inverter chain
and both are driven by an input pulse of 50 MHz with rise time
and fall time of 10 ps each. Under this condition, the transient at
all the 7 nodes (Y1 to Y7) are noted for both the networks as
shown in Fig. 11.
We can clearly observe from the above transient that, the better
voltage margin of CMOS inverter generates almost full swing at its
output comparing to its CS design counterpart. For a certain Vcont,
input (Vin) of CS section in proposed CS-CMOS network is the out-
put of a CMOS inverter and the full swing of Vin corresponds to a
wider modulation of RON4 and RON5, which in turn leads to the
widening of FTR. Also, due to the poor voltage margin, the CS-
inverter chain fails to work for Vcont < ~400 mV in this case, which
is why FTR is found comparably lesser.
5. Performance comparison
The proposed mixed structure delay cell based ring VCO circuit
is compared with some notable prior arts as shown in Table 5. It is
to note that a few previous works achieved good oscillation fre-
quency at the cost of higher power dissipation, low tuning range
and large die area, which makes them vulnerable for modern high
speed on-chip communication circuits. Thus, the proposed circuit
outplays them in terms of performance metrics. The major high-
lights of this new hybrid design are higher oscillation frequency
with ultra-low power dissipation, best tuning range and tiny sili-
con area along with better figure of merit.
6. Validation in lower technology
Continuously increasing scaling factor in VLSI technology

lower technologies correspond to several issues occurred while
analysing the performance metrics. Hence, todays chip needs to
ð14Þ be validated at lower commercial technology to justify its scalabil-
ity. Accordingly, we have taken UMC 28 nm CMOS to design and
simulate our hybrid VCO circuit and the metrics are displayed in
Table 6. It is seen that the circuit is well functional at lower nodes
with superior performance in terms of power burn and oscillation
frequency.
7. Conclusion
A power efficient and PVT tolerant hybrid ring VCO consisting of
basic CMOS inverter and current starved power switching inverter
is explored in this article to note an advantage of 82.66%, 44.85%,
2.79%, 25.81% and 18.02% for fOSC, KVCO, FoM, gate count and FTR
respectively against the current staved design counterpart. This
design doesn’t only offer higher oscillation frequency, but also
works well at a supply as small as 0.6 V. The functionality is tested
under extreme corners for both ‘no skew’ and ‘5% process skew’ to
justify the robustness of the architecture.
From the analyses performed, it may be concluded that our
design has demonstrated its supremacy against the existing works
in terms of almost all performance parameters and claimed its
potential to be adopted in future energy efficient phase locked loop
applications such as radio frequency (RF) and wireless communica-
tion or transceiver circuit design.
Acknowledgments
The authors would like to thank MEITY, Govt. of India for pro-
viding Cadence tool under SMDP C2SD project.
Appendix A
See Table 7.

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx 7

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IETE J Res 2018;64(2):263–9. Pradesh, India. His research interests are Low power
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2009;17(4):571–7.

Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
8 M. Maiti et al. / Ain Shams Engineering Journal xxx (xxxx) xxx
Abir J. Mondal obtained his B-Tech in ECE from
University Institute of Technology, Burdwan University,
India in 2007 and M-Tech in Microelectronics and VLSI
NIT Durgapur, India in 2011 and PhD from NIT Aruna-
chal Pradesh in 2018. He joined the Computer Engi-
neering department of the MNIT Jaipur, India as a
Research Associate in 2011. In 2013, he joined NIT
Arunachal Pradesh, India and currently serves as an
Assistant Professor there. His interest includes Analog
VLSI and Network-on-chip
Please cite this article as: M. Maiti, S. K. Saw, A. J. Mondal et al., A hybrid design approach of PVT tolerant, power efficient ring VCO, Ain Shams Engineering
Journal, https://doi.org/10.1016/j.asej.2019.10.009
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Alak Majumder has completed his PhD degree from
NIT, Arunachal Pradesh, India and is working there as an
Assistant Professor in the Department of ECE. He earned
his M- Tech in Microelectronics & VLSI and BE in Elec-
tronics & Telecommunication Engineering from NIT
Agartala and TIT Agartala. He also served as Assistant
Professor in the Department of ECE at ICFAI University,
Agartala. He has 75+ technical articles, 6 filed Indian
Patents and 1 US Patent to his credit. His current
research interests include Analog-Digital VLSI, Clock
Gating and Distribution and Wireline Communication
Circuit. He is a Member of the IEEE, IAENG and IACSIT.