Microcontrollers An Introduction Features & Applications

MICROCONTROLLERS
An Introduction
Features & Applications
Prof. (Dr.) Anil Kumar
1
Microprocessor
Microprocessor: single chip processor

(control and data Path)
– Processor control
– Register
– Integer Arithmetical and Logic Unit
– Floating Point Arithmetical Unit
– Cache and memory access units
– Other components
Prof. (Dr.) Anil Rose 2
Components of a Microcomputer
Input Output
Device Microprocess Device
or
(acting as
Interrupt CPU) Timing
Handler Unit
Memories

Evolution of Microprocessor
Technology
More powerful processors Integrating all the

with larger data width and necessary components of
greater memory capability a microcomputer on a chip.
8,16, 32, & 64 bit MICROCONTROLLERS

microprocessors.
80386, 80486, Pentium

CPU
Address Bus(16- bit)
Cpu Data Bus(8)
Control Bus(6)
Inter Face Peripheral

RAM ROM Circuit Interface

IR PC
Instruction decode &

Control unit
Registers
ALU

CPU
P Address bus
C
IR Data Bus
RAM
Clock
Read
BUS activity for an opcode fetch cycle

Microcontroller
• Microcontroller is a general purpose device,
meant to read data, perform limited
calculations on that data, and control its
environment based on those calculations.
In 1976 Intel introduce the 8048 as the first single chip

microcontroller.
This was superseded by the 8051 introduced in 1980.

8051
• Today over fifty companies produce variations of
the 8051.
• Several of these companies have over fifty
versions of the 8051.
• 8051 cores are available for implementations in
FPGA’s or ASIC’s.
• Over 100 million 8051’s are sold each year.
• The 8051 has been extremely successful, and has
directly influenced many of the more recent
microcontroller architectures.

MCS-51
• MCS-51 is Intel's designation for its family of 8051
devices.
• The 8051 is the original member of the MCS-51 family,
and is the core for all MCS-51 devices.
• The original 8051 was available in three versions.
– 8051 – A fixed program in ROM version.
– 8031 – No internal ROM program stored in external
PROM memory.
– 8751 – Program stored in internal EPROM. Erased by
exposing the chip to high intensity ultraviolet light for
several minutes. Eventually EPROM was replaced by
EEPROM.

Features of a Microcontrollers
• Inbuilt memories
• I/O ports
• UART
• Timers
• Counters
• Power Down Modes

Features of a Microcontrollers
• ADC
• PWM (DAC)
• Watchdog timer

Introduction to
Microcontrollers
Microprocessors
 CPU only
 Needs many ICs to implement a small system

Introduction to
Microcontrollers
Microcontrollers
 CPU + I/O + Timer(s) [+ ROM] [+ RAM]
 Limited RAM space, ROM space and I/O pins
 EPROM version available
 Low chip-count to implement a small system
 Low-cost at large quantities
Development tools readily available at
reasonable cost

Classification based on number of
bits
• 4 bit (TMS 1000, COP420)
• 8 bit (8048, 8051, 68HC11, Z8, TMS 7500)
• 16 bit ( 80C196, MC68HC12)
• 32 bit (80960, 251 family, ARM processor
based systems)

Classification based on memory
• Embedded microcontrollers
( eg. 8051, 80196, most of the microcontrollers
are Embedded MCs)
• External Memory Microcontrollers
(eg 8031)

Classification based on Instruction
Set
• CISC Architecture MCs (eg. 8096 family)
• RISC Architecture MCs (eg. Intel 80960
family, ARM processor based MCUs)

Classification based on memory
architecture
• Harvard architecture MCs: Distinct address
space for program and data memory (eg. 8051)
• Princeton / Von Neumann architecture MCs:
Common memory address space for program
and data memory (eg. 68HC11)

µC versus µP
µC µP
• Contains internal RAM, ROM, • RAM, ROM I/O ports are
timers, parallel and serial I/O external.
• Completely functional • External digital parts required
• More bit handling instructions to make it functional
• Mostly internal data movement • Lesser bit handling instructions
hence lesser opcodes for • Concerned with external data
external data movement movement
• Special purpose digital • General purpose digital
controller. computers

Significance of IC numbers
• Significance of digit after 8
• 7 : Internal EPROM as program memory
• 3 : Masked ROM as program memory
• 9 : Internal flash as program memory
• Postfix RA/ RB/ RC means 512 B RAM
• C in between indicates that the device is built in
CMOS IC technology.

DAC / PWM
• A unit for obtaining analog output
using the digital bit at an input or at
a register.
• PWM output gives pulse output with
width percentage mapped to the
available digital or analog input or to
get the analog output from the bits
in the register.
Timers and Counters
• Timer increment • Counter is a digital
(or decrement) circuit to count
when the input the input pulses.
clock pulses are • Used for
applied to it after measuring external
suitable scaling. unknown
• It interrupts on frequencies.
timeouts

Watchdog Timer
• A timing device that resets the
system after a predefined timeout.
• It rescues the system if a fault
develops in between when the
program is running eg. When the
program hangs due to an interfaced
circuit fault or loop not exiting due
to an exception.
Power saving modes
• For applications where power
consumption is critical the CMOS
ICs provides power reduced modes
of operation. These are
– Idle Mode
– Power Down Mode

Real Time clock(RTC)
• A clock continuously ticking and
interrupting the system.
• Used for real time control in the
system.

APPLICATIONS
• Peripheral Controller
– Keyboard controller
– LAN controller
– Disk drive Controller
– Printer controller
– DRAM Controller
– DMA controller

APPLICATIONS
• Biomedical Instruments
– ECG LCD display cum recorder
– Patient monitor system
– Blood cell recorder

APPLICATIONS
• Communication Systems
– Pagers
– Cell phones
– Cable TV terminals
– FAX
– Transceivers
– Video games

APPLICATIONS
• Automatic Signal tracker
• Engine control
• Anti-lock braking system
• Electronic smart weight display machine
• CRT display controller
• Spectrum Analyzer
and many more

ARCHITCTURE
of
8051 micro controller
HARDWARE SUMMRAY
In this lecture the hardware architecture of MCS-51 family is
introduced.The 8051, the first device in the family offered
commercially. Its features are summarized below.
4K bytes ROM
128 bytes RAM
Four 8-bit I/O(input/output) ports
Two 16-bit timers
Serial interface
64K external code memory space
64K external data memory space
210 bit-addressable location
4 microseconds multiply/divide
Comparison of MCS – 51 Ics
Other members of the MCS-51 family offer different combinations of on-
chip ROM or EPROM, on-chip RAM, or a third timer.
PART ON-CHIP ON-CHIP TIMERS

NUMBER CODE DATA
MEMORY MEMORY
8051 4K ROM 128 BYTES 2
8031 0K 128 BYTES 2
8751 4K EPROM 128 BYTES 2
8052 8K ROM 256 BYTES 3
8032 0K 256 BYTES 3
8752 8K EPROM 256 BYTES 3
89c51 4K EEPROM 128 BYTES

Prof. (Dr.) Anil Rose
2 32
INT1* * Alternate pin assignments for P1 & P3
INT0*
Timer2(8032/8052)
T2EX*
Timer1 EEPROM
Timer0
128 bytes ROM
Serial port T2*
RAM 0K – 8031/8032 Timer 2
(8032/8052) 4K – 8051 (8032/8052)
Interrupt Other 128 bytes 8K – 8052 Timer 1 T1*
control resisters RAM Timer 0 T0*
CPU
Serial
oscillator Bus control I/O port
port
EA ALE
RST P0Rose
Prof. (Dr.) Anil P2 P1 P3 TXD* 33
RXD*
PSEN (Address/data)
SEMICONDUCTOR MEMORY: RAM AND
ROM
Programs and data are stored in memory. The variation of
computer memory are so vast,their accompanying terms so
plentiful, and technology breakthroughs so frequent, that
extensive and continual study is required to keep abreast of
the latest developments.the memory devices directly
accessible by the CPU consist of semiconductor ICs
(integrated circuits) called RAM and ROM.there are two
features that distinguish RAM and ROM: first, RAM is
read/write memory while ROM is read-only memory, and
second , RAM is volatile (the contents are lost when power
is removed), while ROM is non-volatile.
ACCUMULATOR (ACC): The accumulator resister (ACC or A) acts as
an operand resisters, in case of some instructions. This may either be implicit or
specified in the instruction. The ACC resister has been allotted an address in the
on-chip special function resister bank.
B REGISTER: This resister is used to store one of the operands for multiply
and divide instructions. In other instructions, it may just be used as a scratch pad.
This register is considered as a special function registers.
PROGRAM STATUS WORD (PSW): This set of flags contains the

status information and is considered as one of the special function resisters.
STACK POINTER (SP): This 8-bit wide resister is incremented before the
data is stored onto the stack using push or call instructions. This contains 8-bit
stack top address. The stack may be defined anywhere in the on-chip 128-byte
RAM.
DATA POINTER (DPTR): This 16-bit resister contains a higher
byte (DPH) and the lower byte (DPL) of a 16-bit external data RAM
address. It is accessed as a 16-bit resister or two 8-bit resisters as specified
above. It has been allotted two addresses in the special function resister
bank, for its two bytes DPH and DPL.
PORT 0 TO 3 LATCHES AND DRIVERS : These four

latches and driver pairs are allotted to each of the four on-chip I/O ports.
These latches have been allotted addresses in the special function resister
bank.Using the allotted addresses, the user can communicate with these
ports. These are identified as P0, P1, P2 , and P3.
SERIAL DATA BUFFER: The serial data buffer internally

contains two independent resisters. One of them is a transmit buffer
which is necessarily a parallel-in serial-out resister. The other is called
receive buffer which is a serial-in parallel-out resister. Loading a byte to
the transmit buffer initiates serial transmission of that byte. The serial data
buffer is defined as SBUF and is one of the special function resisters. If a
byte is written to SBUF, it initiates serial transmission and if the SBUF is
read , it reads received serial data.Prof. (Dr.) Anil Rose 36
TIMER REGISTERS: these two 16-bit registers can be accessed as
their lower and upper bytes. For example , TL0 represents the lower byte
of the timing resister 0. Similarly , TL1and TH1 represents the lower and
higher bytes of timing resister 1.
CONTRO; REGISTERS: the special function registers IP , IE ,

TCON , SCON and PCON contains control and status information for
interrupts , timers/counters and serial port. All of these resisters have been
allotted addresses in the special function resister bank of 8051.
TIMING AND CONTROL UNIT: This unit drives all the

necessary timing and control signals required for the internal operation of
the circuit. It also drives control signals required for controlling the
external system bus.
OSCILLATOR: this circuit generates the basic timing clock signal

for the operation of the circuit using crystal oscillator.
INSTRUCTION REGISTER: this register decodes the opcode of
an instruction to be executed and gives information to the timing and
control unit to generate necessary signals for the execution of the
instruction.
EPROM AND PROGRAM ADDRESS REGISTER: these

blocks provide an on-chip EPROM and a mechanism to internally address
it. Note that EPROM is not available in all 8051 versions.
ALU: the arithmetic and logic unit performs 8-bit arithmetic and logical
operations over the operands held by the temporary resisters TMP1 and
TMP2. Users cannot access these temporary resisters.
SFR: this is a set of special function registers , which can be addressed

using their respective addresses which lie in the range 80H to FFH.
Finally , the interrupt , serial port and timer units control and
perform their specific functions under the control of the timing and
control unit. Prof. (Dr.) Anil Rose 38
Pin Description
Port 0 :- it is dual purpose port on pin 32 – 39, it is used as general purpose I/O
port, for larger design with external memory it become multiplexed address and
data bus
Port 1(1-8):- it is dedicated to interfacing to external devices as required. No
alternate function is assigned for port 1. exception are for 8032/8052 P1.0 & P1.1
as a external i/p to third timer
Port2 (21-28):- it is dual purpose port serving as general purpose I/O, or as the
high byte of the address bus for designs with external code memory or more than
256 bytes of external data memory.
Port 3(10-17):- it is also dual purpose port general purpose I/O and these pins are
multifunctional with each having an alternate purpose related to special feature of
8051.
Cont…
Cont….
Bit Name Bit address Alternate
name
P3.0 Rxd 80H receive data for serial port
P3.1 Txd B1H transmitt data for serial port
P3.2 Int0 B2H External Interrupt 0
P3.3 Int1 B3H External Interrupt 1
P3.4 T0 B4H Timer/counter 0 external i/o
P3.5 T1 B5H Timer/counter 1external i/o
P3.6 WR B6H external data memory with
strobe
P3.7 RD B7H external data memory with
strobe
P1.0 T2 90H Timer/counter 2external i/o
P1.1 T2ex 91H Timer/counter 2capture/ reload
Program store enable (PSEN)
It is an output signal on pin 29, it is control signal that enable external memory, it is
usually connect to an EPROM output enable
IR
8051 EPROM
Opcode read from EPROM

ALE (Address Latch Enable)
It is on 30 pin used for demultiplexing the address bus and data bus. When port 0 is
used in its alternate mode –as the data bus and the low bytes of address bus – ALE is the
signal that latches the address into the external register during first half of a memory
cycle and then port 0 is available for the data i/p & o/p during second half.
ALE
ADD DATA
The ALE signal pulses at a rate of 1/6 the on chip oscillator frequency and can be used
as a general purpose clock for the rest of the system. If 8051 is clocked from 12mhz
then ALE oscillate 2mhz.only exception is that during movx when one ALE pulse is
missed this pin is also used for programming i/p pulse for EPROM of the 8051
EA(EXTERNAL ACCESS)
It is I/P signal on pin 31 is generally tied high or low. If high the
8051/8052 execute program from internal ROM and if low programme
execute from external ROM (PSEN will be low). EA must be low for
8031/8032 since there is no on chip memory.if EA is low disable te
internal ROM and programme execute from EPROM. The EPROM
version of 8051 also use EA line for +21 volt supply for programming
the internal EPROM.
EA EPROM
ROM
RST (Reset)
I/P on pin 9 is the master reset for 8051.when the signal is brought high at least for
two machine cycles.8051 internal registers are loaded with appropriate value for an
orderly system start-up.
ON-CHIP OSCILLATOR :- 8051 features an on

chip oscillator that is typically driven by a crystal connected on pin 18 & 19.
stabilizing capacitor are also required. The nominal crystal frequency is 12mhz for
most ICs although 8031 requires 16mhz. The chip oscillator need not be driven by
crystal a TTL clock source can be connected to XTAL1 and XTAL2.
I/O Port Structure
8051 internal bus
read vcc Read
latch Internal pin
Pull up register
D
Port Q
latch
Write to
latch

Cont….
• Writing pin to load the data in the port latch which drive the FET.
• Drive capability ‘4 low schottky TTL loads for port 1,2 & 3.
• 8 LS load for port 0.
• An external pull up register may require depend upon the I/p
characteristic of the device driven.
• There is “both read latch” & “read pin” capability.
• Instruction that requires a read – modify – write operation read the
latch to avoid misinterpreting the voltage level in the event the pin is
heavily loaded.
• Port latch must contain 1, otherwise the FET is on and pulls the o/p
low.

Memory organization

Memory Space

Internal RAM organization
Summary
of the
8051 on-
chip data
memory
(RAM)

Summary
of the
8051 on-
chip data
memory
(Special
Function
Registers)

BASICS
• Microprocessor shared memory space for data and programs.
• Microcontroller rarely used as CPU , instead they are used as control oriented
design .there is limited memory and there is no disk or disk operating system. The
programs must reside in ROM..
• Microcontroller implement separate memory space for code ( Program) and data
• Internal memory consist on chip RAM & ROM.
• Two main feature a) the registers and I/O ports are memory mapped and accessible
like any other memory location. b) the stack reside with in the internal RAM, rather
than external RAM.

GENERAL PURPOSE RAM
• 80bit of GPR from address 30H to 7FH.
• Bottom 32 bit from 00H to 1FH can be used similarly.
• Any location can be accessed freely either directly or indirectly. e.g. Mov A,
5FH,
• Mov Ro, #5FH , Mov A, @ Ro

Bit Addressable RAM
• 210 bit- addressable location, of which 128 are at byte address 20H to 2FH
• Individual accessing of bit through S/W is a powerful feature of most
microcontroller.
• Bits can be set, cleared, AND, OR etc with a single instruction .
• I/O ports are bit addressable
• 20H to 2FH address are accessed either bits or bytes, depending upon
instruction. Eg. SETB 67H

Register Banks
• 8051 instruction set support 8 registers R0 to R7 (00 -07H)
• Instruction using R0 to R7 are shorter and faster than the equivalent
instruction using direct addressing
• The active register bank may be altered by changing the register bank

Special Function Register (SFR)
• In microprocessor most register are accessed implicitly by the instruction set.
E.g. INCA same in microcontroller
• There are 21 SFR defined at the top of internal RAM from 80H –FFH
• Some SFR are both bit & byte addressable designer should be careful
• eg. SETB 0E0H

PSW
CY AC F0 RS1 RS0 OV P
D7H D6H D5H D4H D3H D2H D1H D0H
Over flow
flag0 Even parity
00 –bank0 Reserved
Auxiliary 01 – bank1
Carry 10 - bank2
11 - bank3
Carry flag

Carry Flag
• It is dual purpose used in traditional way for
arithmetic operation: set if there is
carry/borrow out of bit 7 during add and
subtract
• Carry flag is also Boolean accumulator.
Serving as a 1-bit register for Boolean
instructions operating on bits. E.g
• ANL C 25h

Auxiliary Carry Flag
• When BCD values are added, the auxiliary

carry flag set if a carry was generated out of
3 bit into 4 or if the result in lower nibble is
in the range 0AH – 0FH. If the value added
are BCD then add instruction is followed by
DAA (decimal adjust accumulator) to bring
the results greater than 9 back into range.

Flag 0
• It is general purpose flag bit available for
user application.

Register bit selects bits
• The register bank select bit(RS0 –RS1)
determine the active register bank. They are
cleared after a system reset and are changed
by s/w as needed. E.g SETB RS1 Register 3
SETB RS0
Mov A, R7

Overflow Flag
• It is set after an addition or subtraction operation if
there was an arithmetic overflow. When signed are
added or subtracted . S/W can examine this bit to
determine if the result is in the proper range.
When unsigned number are added, the OV bit can
be ignored the result greater then +127 or less than
-128 will set the OV
• E.g. 0F + 7F = 8E (hex) , 15 +127 =142 (decimal)
so here 8E represent -116 which is clearly not a
correct result of 142 so OV is set.
Parity Bit
• It is automatically set or clear each machine
cycle to establish even parity with
accumulator plus to establish even parity
with accumulator, the number of 1-bit in the
accumulator plus the P bit is always even.
The parity bit is most commonly used in
conjunction with serial port routine to
include a parity bit before transmission or to
check the parity after reception.
B Register (F0H)
• It is used along with accumulator for multiply and
divide operations.
• MUL AB – multiply the 8-bit unsigned values in
A and B and leaves the 16-bit results in A (low-
byte) and B (high –byte)
• DIV AB divides A by B leaving the integer results
in A and reminder in B. the register B can also be
used as general purpose scratch pad. It is bit
addressable (F0H – F7H).
Stack Pointer(81H)
• It contain the address of the data item currently on the top of the stack.
• Stack operation includes pushing (writing) data on the
stack( increment the SP before) and popping( reading) data
(decrement the SP)
• In 8051 stack is kept in RAM & is limited to address accessible by
indirect addressing
• To reinitialize the SP with the Stack beginning at 60H following
instruction is used: MOV SP # 5FH
• Designer may choose not to initialize the stack pointer and let it retain
with default value.
• Stack is accessed explicitly by PUSH and POP instruction and
implicitly by subroutine (ACALL & LCALL) and return instruction
(RET ,RET1)

DPTR(82-83H)
• It is used to access the external code and
data memory
• It is 16 –bit register DPL and DPH
• MOV A,#55H
MOV DPTR,#1000H
MOVX @, A

Port Register
• Port0 at 80H, Port1 at 90H, Port2 at A0H,
Port3 at B0H,
• port 0, 2 & 3 may not available for I/O if
external memory or special feature are used.
• All ports are bit addressable

Timer Register (8AH – 8DH)
• It contain two 16 –bit timer/counter for timing
interval or counting events.
• Events Timer0 is at 8AH(TL0, Low byte) and
8CH(TH0, high byte) and Timer1 is at 8BH(TL1,
Low byte) and 8DH (TH1, high byte)
• Timer operation is set by timer mode register
(TMOD) at 89H and timer control (TCON) at 88H
and only TCON is bit addressable.

Serial Port Register
• 8051 contain on –chip serial port for
communication with serial devices
( modems or terminals) or for interface with
other ICs.
• One register SBUF at 99H, it holds both
transmitting and receiving the data.
• SCON at 98H to perform various
programmable operations

Interrupt Register
• 8051 has 5 source, 2 priority level interrupt
structure.
• Interrupt are disable after system are reset
and enable by writing to the interrupt enable
register IE at A8H
• Priority is set through IP register at B8H

Power Control Register
SMOD ---- ---- ----- GF1 GF0 PD IDL
Double baud rate bit:

General Idle mode:
When set, baud rate is purpose Gen Power
eral down set to
Doubled in serial port flag bit 1 activate
purp mode: set
Modes 1,2&3 ose to activate idle mode,
flag Power only exist
bit 0 down , is an
only exist interrupt or
Prof. (Dr.) Anil Rose is reset system
71
reset
External Memory

• Microcontroller have inbuilt capability to
expand the on chip source
• . Microcontroller provides an option 64 k
data and code memory expansion.
• Extra RAM and ROM can be added as per
desire

8051 Timers
• The 8051 has two timers/counters, they can be
used as
– Timers to generate a time delay
– Event counters to count events happening outside the
microcontroller
• Both Timer 0 and Timer 1 are 16 bits wide
– Since 8051 has an 8-bit architecture, each 16-bits
timer is accessed as two separate registers of low
byte and high byte
Timer 0 & 1 Registers
• Accessed as low byte and high byte

– The low byte register is called TL0/TL1
– The high byte register is called TH0/TH1
– Accessed like any other register
MOV TL0,#4FH
MOV R5,TH0

TMOD Register
• Both timers 0 and 1 use the same register,

called TMOD (timer mode), to set the
various timer operation modes
– TMOD is a 8-bit register
• The lower 4 bits are for Timer 0
• The upper 4 bits are for Timer 1
– In each case, the lower 2 bits are used to set the timer
mode
– The upper 2 bits to specify the operation

GATE
• Timers of 8051 do starting and stopping by
either software or hardware control
– In using software to start and stop the timer where
GATE=0
• The start and stop of the timer are controlled by way of
software by the TR (timer start) bits TR0 and TR1
• The SETB instruction starts it, and it is stopped by the
CLR instruction
– These instructions start and stop the timers as long as GATE=0
in the TMOD register

GATE (cont.)
• The hardware way of starting and stopping

the timer by an external source is achieved
by making GATE=1 in the TMOD register

Mode 1 Programming
• The following are the characteristics and
operations of mode1:
– It is a 16-bit timer
• It allows value of 0000 to FFFFH to be loaded into
the timer’s register TL and TH
– After TH and TL are loaded with a 16-bit initial
value, the timer must be started
• This is done by SETB TR0 for timer 0 and SETB
TR1 for timer 1
– After being started, it starts to count up
• It counts up until it reaches its limit of FFFFH
Mode 1 Programming (cont.)
• When it rolls over from FFFFH to 0000, it sets high
a flag bit called TF (timer flag)
– Each timer has its own timer flag: TF0 for timer 0, and
TF1 for timer 1
– This timer flag can be monitored
• When this timer flag is raised, one option would be
to stop the timer with the instructions CLR TR0 or
CLR TR1, for timer 0 and timer 1, respectively
– In order to repeat the process
• TH and TL must be reloaded with the original
value
• TF must be reloaded to 0

Steps to Mode 1 Program
• Load the TMOD value register
– Indicating which timer (timer 0 or timer 1) is to be
used and which timer mode (1 or 2) is selected
• Load registers TL and TH with initial count value
• Start the timer
• Keep monitoring the timer flag (TF)
– With the JNB TFx,target instruction to see if it is
raised

Steps to Mode 1 Program (cont.)
– Get out of the loop when TF becomes high
• Stop the timer
• Clear the TF flag for the next round
• Go back to Step 2 to load TH and TL again

If TH and TL are not reloaded. the program generates a
single pulse.
Finding the Loaded Timer Values
• To calculate the values to be loaded into the

TL and TH registers:
– Assume XTAL = 11.0592 MHz
• Divide the desired time delay by 1.085 us
• Perform 65536 – n, where n is the decimal value we
got in Step1
• Convert the result of Step2 to hex, where yyxx is the
initial hex value to be loaded into the timer’s register
• Set TL = xx and TH = yy
CPL P1.5 ; Comp. P1.5 to get Hi, Lo

CPL P2.3 ; Comp. P2.3 to get Hi, Lo
CLR TF1 ; Clear timer 1 flag
SJMP AGAIN ;Reload timer
Mode 2 Programming
• The following are the characteristics and
operations of mode 2:
– It is an 8-bit timer
• It allows only values of 00 to FFH to be loaded into the
timer’s register TH
– After TH is loaded with the 8-bit value, the 8051
gives a copy of it to TL
• Then the timer must be started
– This is done by the instruction SETB TR0 for timer 0 and SETB
TR1 for timer 1

– After the timer is started, it starts to count up by
incrementing the TL register
• It counts up until it reaches its limit of FFH
• When it rolls over from FFH to 00, it sets high the TF
(timer flag)
– When TF is set to 1, TL is reloaded automatically
with the original value kept by the TH register
– To repeat the process, we must simply clear TF and
let it go without any need by the programmer to
reload the original value
• Mode 2 can auto-reload, in contrast with

mode 1 in which the programmer has to
reload TH and TL

Steps to Mode 2 Program
• Load the TMOD value register
– Indicating which timer (timer 0 or timer 1) is to be
used, and the timer mode (mode 2) is selected
• Load the TH registers with the initial count value
• Start timer
• Keep monitoring the timer flag (TF)
– With the JNB TFx,target instruction to see whether it
is raised

Steps to Mode 2 Program (cont.)
– Get out of the loop when TF goes high
• Clear the TF flag
• Go back to Step 4
– Since mode 2 is auto-reload

(25
The number 200 is
the timer count till 3)
the TF is set to 1
Counter Programming
• Timers can also be used as counters
– Counting events happening outside the 8051
– A pulse outside of the 8051 increments the TH, TL
registers
– TMOD and TH, TL registers are the same as for the timer
• Programming the timer also applies to programming it as a
counter
– Except the source of the frequency
– The C/T bit in the TMOD registers decides the source of
the clock for the timer

Counter Programming (cont.)
• When C/T = 1, the timer is used as a counter and
gets its pulses from outside the 8051
– The counter counts up as pulses are fed from
pins 14 and 15
• These pins are called T0 (timer 0 input) and T1
(timer 1 input)

TCON Register
• TCON (timer control) register is an 8-bit

register

TCON Register (cont.)
• TCON register is a bit-addressable register

Case of GATE = 1
• The start and stop of the timer are done
externally through pins P3.2 and P3.3 for
timers 0 and 1, respectively
– Allows to start or stop the timer externally at
any time via a simple switch

Interrupts vs. Polling
• An interrupt is an external or internal event
that interrupts the microcontroller
– To inform it that a device needs its service
• A single microcontroller can serve several
devices by two ways
– Interrupts
• Whenever any device needs its service, the device
notifies the microcontroller by sending it an interrupt
signal
• Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device

Interrupts vs. Polling (cont.)
– The program which is associated with the interrupt is called
the interrupt service routine (ISR) or interrupt handler
– Polling
• The microcontroller continuously monitors the status
of a given device
– ex. JNB TF, target
• When the conditions met, it performs the service
• After that, it moves on to monitor the next device
until every one is serviced
– Polling can monitor the status of several devices and serve
each of them as certain conditions are met
• The polling method is not efficient, since it wastes
much of the microcontroller’s time by polling devices
that do not need service
Interrupts vs. Polling (cont.)
• The advantage of interrupts is:
– The microcontroller can serve many devices
(not all at the same time)
• Each device can get the attention of the
microcontroller based on the assigned priority
• For the polling method, it is not possible to assign
priority since it checks all devices in a round-
robin fashion
– The microcontroller can also ignore (mask) a
device request for service
• This is not possible for the polling method

Interrupt Service Routine
• For every interrupt, there must be an
interrupt service routine (ISR), or
interrupt handler
– When an interrupt is invoked, the
microcontroller runs the interrupt service
routine
– There is a fixed location in memory that
holds the address of its ISR
• The group of memory locations set aside to hold
the addresses of ISRs is called interrupt vector
table
Steps in Executing an Interrupt
• Upon activation of an interrupt, the
microcontroller goes through:
– It finishes the instruction it is executing and
saves the address of the next instruction (PC)
on the stack
– It also saves the current status of all the
registers internally (not on the stack)
– It jumps to a fixed location in memory, called
the interrupt vector table, that holds the
address of the ISR

Steps in Executing an Interrupt
(cont.)
– It gets the address of the ISR from the interrupt
vector table and jumps to ISR
• It starts to execute the interrupt service subroutine
until it reaches the last instruction of the subroutine
which is RETI (return from interrupt)
– Upon executing the RETI instruction, the
microcontroller returns to the place where it was
interrupted
• It gets the program counter (PC) address from the
stack by popping the top two bytes of the stack into
the PC
• It starts to execute from that address
Six Interrupts in 8051
• Six interrupts are allocated as follows
– Reset – power-up reset
– Two interrupts are set aside for the timers:
• One for timer 0 and one for timer 1
– Two interrupts are set aside for hardware external
interrupts
• P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)
– Serial communication has a single interrupt that belongs
to both receive and transfer
Enabling and Disabling an Interrupt
• Upon reset, all interrupts are disabled

(masked)
– None will be responded to by the microcontroller
if they are activated
• The interrupts must be enabled by software in order
for the microcontroller to respond to them
– There is a register called IE (interrupt enable)
that is responsible for enabling (unmasking) and
disabling (masking) the interrupts
Enabling and Disabling an Interrupt
(cont.)
• To enable an interrupt, we take the
following steps:
– Bit D7 of the IE register (EA) must be set to
high to allow the rest of register to take effect
– The value of EA
• If EA = 1, interrupts are enabled and will be
responded to if their corresponding bits in IE are
high
• If EA = 0, no interrupt will be responded to, even
if the associated bit in the IE register is high
Timer Interrupts
• The timer flag (TF) is raised when the timer
rolls over
– In polling TF, we have to wait until the TF is
raised
• The microcontroller is tied down while waiting for TF to
be raised, and can not do anything else
– Using interrupts to avoid tying down the controller
• If the timer interrupt in the IE register is enabled,
whenever the timer rolls over, TF is raised

Timer Interrupts (cont.)
• The microcontroller is interrupted in whatever it is
doing, and jumps to the interrupt vector table to
service the ISR
• In this way, the microcontroller can do other until it
is notified that the timer has rolled over

SETB
P2.1

External Hardware Interrupts
• The 8051 has two external hardware
interrupts
– Pin 12 (P3.2) and pin 13 (P3.3) of the 8051
• Designated as INT0 and INT1
• Used as external hardware interrupts
– The interrupt vector table locations 0003H and
0013H are set aside for INT0 and INT1
– There are two activation levels for the external
hardware interrupts
• Level trigged
• Edge trigged
Level-Triggered Interrupt
• INT0 and INT1 pins are normally high
– If a low-level signal is applied to them, it
triggers the interrupt
• The microcontroller stops whatever it is doing and
jumps to the interrupt vector table to service that
interrupt
• The low-level signal at the INT pin must be
removed before the execution of the last
instruction of the ISR, RETI
– Otherwise, another interrupt will be generated
• This is called a level-triggered or level-activated
interrupt and is the default mode upon reset
Sampling Low Level-Triggered
Interrupt
• P3.2 and P3.3 are used for normal I/O
– Unless the INT0 and INT1 bits in the IE register
are enabled
• After the hardware interrupts are enabled, the
controller keeps sampling the INTn pin for a low-level
signal once each machine cycle
• The pin must be held in a low state until the start of
the execution of ISR
– If the INTn pin is brought back to a logic high before the
start of the execution of ISR, there will be no interrupt
• If INTn pin is left at a logic low after the RETI
instruction of the ISR, another interrupt will be
activated after one instruction is executed
Sampling Low Level-Triggered
Interrupt (cont.)
• To ensure the activation of the hardware
interrupt at the INTn pin,
– The duration of the low-level signal is around
4 machine cycles, but no more
• This is due to the fact that the level-triggered
interrupt is not latched
• Thus the pin must be held in a low state until the
start of the ISR execution

Edge-Triggered Interrupt
• To make INT0 and INT1 edge-triggered
interrupts, we must program the bits of the
TCON register
– The TCON register holds the IT0 and IT1
flag bits that determine level- or edge-
triggered mode of the hardware interrupt
• IT0 and IT1 are bits D0 and D2 of TCON
– They are also referred to as TCON.0 and TCON.2 since
the TCON register is bit-addressable

Sampling Edge-Triggered Interrupt
• The external source must be held high for
at least one machine cycle, and then held
low for at least one machine cycle
– The falling edge of pins INT0 and INT1 are
latched by the 8051 and are held by the
TCON.1 and TCON.3 bits of TCON register
• Function as interrupt-in-service flags
• It indicates that the interrupt is being serviced
now
– On this INTn pin, no new interrupt will be responded to
until this service is finished
Sampling Edge-Triggered Interrupt
(cont.)
• When the ISRs are finished, TCON.1 and
TCON.3 are cleared
– The interrupt is finished and the 8051 is ready
to respond to another interrupt on that pin
• During the time that the interrupt service routine is
being executed, the INTn pin is ignored, no matter
how many times it makes a high-to-low transition
– RETI clears the corresponding bit in TCON
register (TCON.1 or TCON.3)
• There is no need for instruction CLR TCON.1
before RETI in the ISR associated with INT0
Serial Communication Interrupt
• TI (transfer interrupt) is raised when the stop
bit is transferred
– Indicating that the SBUF register is ready to transfer
the next byte
• RI (received interrupt) is raised when the stop
bit is received
– Indicating that the received byte needs to be picked
up before it is lost (overrun) by new incoming serial
data
RI and TI Flags and Interrupts
• In the 8051 there is only one interrupt set
aside for serial communication
– Used to both send and receive data
– If the interrupt bit in the IE register (IE.4) is
enabled, when RI or TI is raised the 8051 gets
interrupted and jumps to memory location
0023H to execute the ISR
• In that ISR we must examine the TI and RI flags
to see which one caused the interrupt and respond
accordingly

Use of Serial COM in 8051
• The serial interrupt is used mainly for
receiving data and is never used for sending
data serially
– This is like getting a telephone call in which we
need a ring to be notified
– If we need to make a phone call there are other
ways to remind ourselves and there is no need
for ringing
– However in receiving the phone call, we must
respond immediately no matter what we are
doing or we will miss the call
TRANS: RETI
END
HERE: JNB TI, HERE
CLR TI
SJMP BACK
TRANS: RETI
END

Interrupt Flag Bits
• The TCON register holds four of the

interrupt flags in the 8051
• The SCON register has the RI and TI flags

Interrupt Priority
• When the 8051 is powered up, the
priorities are assigned
– In reality, the priority scheme is nothing but
an internal polling sequence in which the
8051 polls the interrupts in the sequence
listed and responds accordingly

Altering Interrupt Priority
• We can alter the sequence of interrupt
priority by programming a register called
IP (interrupt priority)
– To give a higher priority to any of the
interrupts, we make the corresponding bit in
the IP register high
– When two or more interrupt bits in the IP
register are set to high
• While these interrupts have a higher priority than
others, they are serviced according to the sequence
of Table 11-13
External Interrupt 1
(INT1)

Interrupt inside an Interrupt
• In the 8051 a low-priority interrupt can be

interrupted by a higher-priority interrupt but
not by another low priority interrupt
– Although all the interrupts are latched and kept
internally, no low-priority interrupt can get the
immediate attention of the CPU until the 8051
has finished servicing the high-priority
interrupts

Triggering Interrupt by Software
• To test an ISR by way of simulation can be done
with simple instructions to set the interrupts high
– Thereby cause the 8051 to jump to the interrupt vector
table
– ex. If the IE bit for timer 1 is set, an instruction such
as SETB TF1 will interrupt the 8051 in whatever it is
doing and will force it to jump to the interrupt vector
table
• We do not need to wait for timer 1 go roll over to have an
interrupt
Basics of Serial Communication
• Computers transfer data in two ways:

– Parallel
• Often 8 or more lines (wire conductors) are used to
transfer data to a device that is only a few feet away
– Serial
• To transfer to a device located many meters away,
the serial method is used
– The data is sent one bit at a time

(cont.)
– At the transmitting end, the byte of data must
be converted to serial bits
• Using a parallel-in-serial-out shift register
– At the receiving end, the serial data is received
and packed into byte
• Using a serial-in-parallel-out shift register

(cont.)
– When the distance is short, the digital signal
can be transferred as it is on a simple wire and
requires no modulation
– If data is to be transferred on the telephone line,
it must be converted from 0s and 1s to audio
tones
• This conversion is performed by a device called a
modem, “Modulator/demodulator”

(cont.)
• Serial data communication uses two methods:
– Synchronous method transfers a block of data at
a time
– Asynchronous method transfers a single byte at a
time
• It is possible to write software to use either of
these methods
– The programs can be tedious and long

(cont.)
• There are special IC chips made by many
manufacturers for serial communications:
– UART (universal asynchronous receiver
transmitter)
– USART (universal synchronous asynchronous
receiver transmitter)

Half- and Full-Duplex Transmission
• If data can be transmitted and received, it is

a duplex transmission
– If data transmitted one way a time, it is referred
to as half duplex
– If data can go both ways at a time, it is full
duplex
• This is contrast to simplex transmission

Start and Stop Bits
• A protocol is a set of rules agreed by both the
sender and receiver on:
– How the data is packed
– How many bits constitute a character
– When the data begins and ends
• Asynchronous serial data communication is
widely used for character-oriented transmissions
– Each character is placed in between start and stop bits,
this is called framing
Start and Stop Bits (cont.)
• The start bit is always one bit
• The stop bit can be one or two bits
• The start bit is always a 0 (low)
• The stop bit(s) is 1 (high)
• Block-oriented data transfers use the
synchronous method

• Due to the extended ASCII characters, 8-bit
ASCII data is common
– In older systems, ASCII characters were 7-bit
• In modern PCs the use of one stop bit is
standard
– In older systems, two stop bits were used
• Due to the slowness of the receiving mechanical device
• To give the device sufficient time to organize itself before
transmission of the next byte
• Assuming that we are transferring a text file of
ASCII characters using 1 stop bit
– We have a total of 10 bits for each character
• This gives 20% overhead
• In some systems, to maintain data integrity, the
parity bit of the character byte is included in the
data frame
– UART chips allow programming of the parity bit for
odd-, even-, and no-parity options
Data Transfer Rate
• The rate of data transfer in serial data
communication is stated in bps (bits per
second)
• Another widely used terminology for bps is
baud rate
– It is modem terminology and is defined as the
number of signal changes per second
• In modems, there are occasions when a single change of
signal transfers several bits of data
Data Transfer Rate (cont.)
– As far as the conductor wire is concerned, the baud
rate and bps are the same
• The data transfer rate of given computer
system depends on communication ports
incorporated into that system
– IBM PC/XT could transfer data at the rate of 100
to 9600 bps
– Pentium-based PCs transfer data at rates as high as
56K bps
– In asynchronous serial data communication, the
baud rate is limited to 100K bps
RS232 Standards
• An interfacing standard RS232 was set by the
Electronics Industries Association (EIA) in
1960
– The standard was set long before the advent of the
TTL logic family, its input and output voltage
levels are not TTL compatible
– A 1 is represented by -3 ~ -25 V
– A 0 bit is +3 ~ +25 V
• Making -3 to +3 undefined
RS232 Standards (cont.)
• Since not all pins are used in PC cables,
IBM introduced the DB-9 version of the
serial I/O standard

Data Communication Classification
• Current terminology classifies data
communication equipment as:
– DTE (data terminal equipment)
• Terminal and computers that send and receive
data
– DCE (data communication equipment)
• Communication equipment, such as modems
• The simplest connection between a PC
and microcontroller at least requires:
– Three pins, TxD, RxD, and ground
RS232 Pins
• DTR (data terminal ready)

– When terminal is turned on, it sends out signal
DTR to indicate that it is ready for
communication
• DSR (data set ready)
– When DCE is turned on and has gone through
the self-test, it assert DSR to indicate that it is
ready to communicate
RS232 Pins (cont.)
• RTS (request to send)

– When the DTE device has byte to transmit, it
asserts RTS to signal the modem that it has a
byte of data to transmit
• CTS (clear to send)
– When the modem has room for storing the data
it is to receive, it sends out signal CTS to DTE
to indicate that it can receive the data now
RS232 Pins (cont.)
• DCD (data carrier detect)
– The modem asserts signal DCD to inform the DTE
that a valid carrier has been detected and that contact
between it and the other modem is established
• RI (ring indicator)
– An output from the modem and an input to a PC
indicates that the telephone is ringing
– It goes on and off in synchronous with the ringing
sound
8051 Connection to RS232
• A line driver such as the MAX232 chip is
required to convert RS232 voltage levels to
TTL levels, and vice versa
• 8051 has two pins that are used specifically
for transferring and receiving data serially
– These two pins are called TxD and RxD
• Part of the port 3 group (P3.0 and P3.1)
• These pins are TTL compatible
– They require a line driver to make them RS232
compatible

MAX233
• To save board space, some designers use
MAX233 chip from Maxim
– MAX233 performs the same job as MAX232
• But eliminates the need for capacitors
• MAX233 and MAX232 are not pin compatible

Serial Communication Programming
• To allow data transfer between the PC and
an 8051 system without any error
– The baud rate of 8051 system must match the
baud rate of the PC’s COM port

SBUF Register
• SBUF is an 8-bit register used solely for
serial communication
– For a byte data to be transferred via the TxD
line, it must be placed in the SBUF register
• The moment a byte is written into SBUF, it is
framed with the start and stop bits and transferred
serially via the TxD line
– SBUF holds the byte of data when it is
received by 8051 RxD line
• When the bits are received serially via RxD, the
8051 deframes it by eliminating the stop and start
bits, and then placing the byte in SBUF
SCON Register
• SCON is an 8-bit register used to program
the start bit, stop bit, and data bits of data
framing, among other things

SCON Register (cont.)
• SM0, SM1
– They determine the framing of data by
specifying the number of bits per character, and
the start and stop bits
• SM2
– This enables the multiprocessing capability of
the 8051
• REN (receive enable)
– When it is high, it allows 8051 to receive data
on RxD pin
– If low, the receiver is disable
• TI (transmit interrupt)
– When 8051 finishes the transfer of 8-bit
character
• It raises TI flag to indicate that it is ready to
transfer another byte
• TI bit is raised at the beginning of the stop bit
• RI (receive interrupt)
– When 8051 receives data serially via RxD, it
gets rid of the start and stop bits and places
the byte in SBUF register
• It raises the RI flag bit to indicate that a byte has
been received and should be picked up before it is
lost
• RI is raised halfway through the stop bit
• SCON is a bit-addressable register

Programming Serial Data
Transmitting
• In programming the 8051 to transfer
character bytes serially
– TMOD register is loaded with the value 20H
• Indicating the use of timer 1 in mode 2 (8-bit auto-
reload) to set baud rate
– The TH1 is loaded with one of the values to
set baud rate for serial data transfer
– SCON register is loaded with the value 50H
• Indicating serial mode 1, where an 8-bit data is
framed with start and stop bits
Programming Serial Data
Transmitting (cont.)
– TR1 is set to 1 to start timer 1
– TI is cleared by CLR TI instruction
– The character byte to be transferred serially is
written into SBUF register
– The TI flag bit is monitored with the use of
instruction JNB TI, xx to see if the character
has been transferred completely
– To transfer the next byte, go to step 5

Importance of TI Flag
• The steps that 8051 goes through in
transmitting a character via TxD
– The byte character to be transmitted is written
into the SBUF register
– The start bit is transferred
– The 8-bit character is transferred on bit at a time
– The stop bit is transferred
• It is during the transfer of the stop bit that 8051
raises the TI flag
– Indicating that the last character was transmitted

Importance of TI Flag (cont.)
– By monitoring the TI flag, we make sure that
we are not overloading the SBUF
• If we write another byte into the SBUF before TI is
raised, the untransmitted portion of the previous
byte will be lost
– After SBUF is loaded with a new byte, the TI
flag bit must be forced to 0 by CLR TI
• In order for this new byte to be transferred
• By checking the TI flag bit, we know
whether or not the 8051 is ready to transfer
another byte
Importance of TI Flag (cont.)
• It must be noted that TI flag bit is raised by
8051 itself when it finishes data transfer
– It must be cleared by the programmer with
instruction CLR TI
• If we write a byte into SBUF before the TI flag bit
is raised, we risk the loss of a portion of the byte
being transferred
– The TI bit can be checked by
• The instruction JNB TI, xx
• Using an interrupt

Programming Serial Data Receiving
• In programming the 8051 to receive character bytes
serially
– TMOD register is loaded with the value 20H
• Indicating the use of timer 1 in mode 2 (8-bit auto-reload) to
set baud rate
– TH1 is loaded to set baud rate
– SCON register is loaded with the value 50H
• Indicating serial mode 1, where an 8-bit data is framed with
start and stop bits
– TR1 is set to 1 to start timer 1
Programming Serial Data Receiving
(cont.)
– RI is cleared by CLR RI instruction
– The RI flag bit is monitored with the use of
instruction JNB RI,xx to see if an entire
character has been received yet
– When RI is raised, SBUF has the byte, and its
contents are moved into a safe place
– To receive the next character, go to step 5

MOVC

Importance of RI Flag
• In receiving bit via its RxD pin, 8051 goes
through the following steps
– It receives the start bit
• Indicating that the next bit is the first bit of the
character byte it is about to receive
– The 8-bit character is received one bit at a time
– The stop bit is received
• When receiving the stop bit 8051 makes RI = 1,
– Indicating that an entire character byte has been received
and must be picked up before it gets overwritten by an
incoming character

Importance of RI Flag (cont.)
– By checking the RI flag bit when it is raised
• We know that a character has been received and is
sitting in the SBUF register
– We copy the SBUF contents to a safe place in some other
register or memory before it is lost
– After the SBUF contents are copied, the RI flag
bit must be forced to 0 by CLR RI
• In order to allow the next received character byte to
be placed in SBUF
– Failure to do this causes loss of the received character
• By checking the RI flag bit, we know when

the 8051 has received a character byte
Importance of RI Flag (cont.)
– If we failed to copy SBUF into a safe place, we
risk the loss of the received byte
– It must be noted that RI flag bit is raised by 8051
when it finish receive data
– It must be cleared by the programmer with
instruction CLR RI
– If we copy SBUF into a safe place before the RI
flag bit is raised, we risk copying garbage
• The RI bit can be checked by
– The instruction JNB RI, xx
– Using an interrupt
Doubling Baud Rate
• There are two ways to increase the baud
rate of data transfer
– To use a higher frequency crystal
• The system crystal is fixed
– To change a bit in the PCON register
• PCON register is an 8-bit register
– It is not a bit-addressable register
• When 8051 is powered up, SMOD is zero
• We can set it to high by software and thereby
double the baud rate

TI, H_1
A_1

Programming the Second Serial
Port
• Many new generations of 8051
microcontroller have two serial ports
– Like DS89C4x0 and DS80C320
– The second serial port of DS89C4x0 uses pins
P1.2 and P1.3 for the Rx and Tx lines
– The second serial port uses some reserved SFR
addresses for the SCON and SBUF
• There is no universal agreement among the makers as
to which addresses should be used
• The SFR addresses of C0H and C1H are set aside for
SBUF and SCON of DS89C4x0
Port (cont.)
• The DS89C4x0 technical documentation refers to
these registers as SCON1 and SBUF1
• The first ones are designated as SCON0 and
SBUF0
• Upon reset, DS89c4x0 uses Timer 1 for setting
baud rate of both serial ports

Port (cont.)
– While each serial port has its own SCON and SBUF
registers
– SBUF and SCON refer to the SFR registers of
the first serial port
– Since the older 8051 assemblers do not
support this new second serial port, we need
to define them in program
• To avoid confusion, in DS89C4x0 programs we
use SCON0 and SBUF0 for the first and SCON1
and SBUF1for the second serial ports

SBUF1 EQU 0C1H
SJMP FN Prof. (Dr.) Anil Rose 220

SJMP LN

Real Time Interfacing
• Processor process data.
memory storage
buses communication
• Communication: transfer of data among
processors and memories.
• This communication is known as
interfacing.
Basic Terminology
unidirectional (rd’/wr , enable) rd'/wr
Processor Memory
• Wires enable
addr[0-11]
bidirectional (data) data[0-7]
• A set of wires with the same function : bus

bus structure
a set of wires with a single function (data bus).
• Bus
entire wires collection along with their communication protocol.
• Protocol: rules for communicating over the wires. (low level HW protocols)
Basic Terminology
• Port: the actual conducting device (metal) on the processor (or
memory) through which the signal is input to, or output from.
• We could use the term pin to refer to a port on a processor.
– Pin is also a term referring to the extending pins from the processor ( as
own IC package). They are designed to be plugged into a socket on a
printed-circuit board.
– Small metallic balls could be used rather than pins( if the processor is
packaged in its own IC ).
• If the processor coexists on a single IC with other processors and
memories, pads of metal are used in the IC.

Timing diagram
rd'/wr rd'/wr
enable enable
addr addr
data
data
tsetup tread
read protocol
tsetup twrite
write protocol
• It is the most common method for describing a HW protocol.

– Time proceeds to the right along the x-axis.
– Control lines high or low.
– Data lines (addr, data) invalid (one horizontal line) or valid (two horizontal lines).
• The processor must place the address on addr for at least tsetup time before setting the enable
high.
• The high enable line triggers the memory to put data on the data wires after tread time.
• When line is active (high, or commonly low) , it triggers the data transfer.
• Assert means setting control line to its active value.
• Deassert means setting control line to its low value.
• A protocol could be consisted of subprotocols (i.e. read, write), known as transaction or a
bus cycle.
cycle A bus cycle may consists of several clock cycles.
Basic protocol concepts
• Actor:
Actor is the processor or memory involved in data transfer.
• A protocol involves two actors: a master, and a servant (slave).
• A master initiates the data transfer (usually general-purpose
processor), and the servant responds to the initiation request (usually
memories and peripherals).
• Data direction:
direction the direction that the transferred data moves btw.
actors( receiving or sending data).
• Addresses:
Addresses a special type of data used to indicate where regular data
should go to or come from (used to address memory locations ,
peripherals and peripheral's registers).

Time multiplexing
– Share a single set of wires for multiple pieces of data.

– Saves wires at expense of time.
Time-multiplexed data transfer
Master req Servant Master req Servant
data(15:0) data(15:0)
addr data addr data
mux demux mux demux

data(8) addr/data
req req
data 15:8 7:0 addr/data addr data
data serializing address/data muxing

Control methods :strobe and handshake
Master Servant Master req Servant
req
ack
data data
req 1 3
req 1 3
data 2 4 ack 2 4
data
taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack
3. Master receives data and deasserts req 3. Master receives data and deasserts req
4. Servant ready for next request 4. Servant ready for next request
Strobe protocol Handshake protocol
• A handshake protocol can adjust to a servant with varying response times, but it
could be slower, and need extra clock cycles and extra line.
Control methods :strobe / handshake
compromise
Master req Servant
wait
data
req 1 3 req 1 4
wait wait 2 3
data 2 4 data 5
taccess taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant can't put data within taccess, asserts wait ack
(wait line is unused) 3. Servant puts data on bus and deasserts wait
3. Master receives data and deasserts req 4. Master receives data and deasserts req
4. Servant ready for next request 5. Servant ready for next request
Fast-response case Slow-response case
• It achieves both the speed of strobe protocol, and the varying response time tolerance of a
handshake protocol.
• The handshake only occurs if it necessary.
The ISA bus protocol – Memory Access
• ISA:
ISA The Industry Standard Microprocessor Memory I/O Device
Architecture.
ISA bus
C1 C2 WAIT C3 C4
•
CYCLE
80x86 microprocessor. CLOCK
•
D[7-0]
20 bit memory address.

DATA
A[19-0]
ADDRESS
• ALE: Address Latch Enable.

ALE
/MEMR
• CHRDY: Channel Ready. CHRDY
• Compromise strobe/handshake CYCLE C1 C2 WAIT C3 C4

control method is used. CLOCK
• The memory deasserted

D[7-0]
A[19-0]
DATA
ADDRESS
CHRDY before the rising clock ALE
/MEMW
edge in C2, causing the CHRDY
microprocessor to insert wait

cycles (up to 6 cycles) until Prof.
CHRDY was reasserted.
(Dr.) Anil Rose 230
Microprocessor interfacing: I/O addressing
• The microprocessor's pins used to communicate data to and from
it, are called I/O pins.
• We normally consider the access to peripherals (not memory), as
I/O.
• Two common methods for using pins to support I/O : Port-based
I/O (Parallel I/O), and Bus-based I/O.
• In parallel I/O , a port can be directly read and written by
processor instructions, like any register.
• Ex.P0=255, g=P2 .
• Ports are often bit-addressable.
• In bus-based I/O, the microprocessor has a set of address, data,
and control ports corresponding to bus lines, and uses the bus to
access memory and peripherals.

Extensions
• Parallel I/O peripheral. Processor Memory
– When processor only supports bus-based I/O

System bus
but parallel I/O needed.
– Each port on peripheral connected to a register within Parallel I/O peripheral
peripheral. The microprocessor can read/write those

registers. Port A Port B Port C
Adding parallel I/O to a bus-

• Extended parallel I/O.
I/O based I/O processor
– When processor supports port-based I/O
but more ports needed. Processor Port 0
Port 1
– One or more processor ports interface with Port 2
Port 3
parallel I/O peripheral extending total number

Parallel I/O peripheral
of ports available for I/O.
– e.g., extending 4 ports to 6 ports in figure.
Port A Port B Port C
Extended parallel I/O

Memory-Mapped I/O and Standard I/O
• They are two bus-based methods for microprocessor to communicate with peripherals.
• In memory-mapped I/O, peripherals occupy specific addresses in the existing address

space.
• e.g., Bus has 16-bit address, lower 32K addresses may correspond to memory, and
upper 32k addresses may correspond to peripherals.
• In standard I/O (I/O-mapped I/O), the bus includes an additional pin (M`/IO), to
include whether the access is to memory or peripheral.
• e.g., Bus has 16-bit address, all of them for memory addressing if M`/IO=0, and all of
them for I/O addressing if M`/IO=1.

Memory-Mapped I/O Vs. Standard I/O
• Memory-mapped I/O
– Requires no special instructions
• Assembly instructions involving memory like MOV and ADD
work with peripherals as well.
• Standard I/O requires special instructions (e.g., IN, OUT) to
move data between peripheral registers and memory.
• Standard I/O
– No loss of memory addresses to peripherals.
– Simpler address decoding logic in peripherals possible.
• When number of peripherals much smaller than address space
then high-order address bits can be ignored
– smaller and/or faster comparators.

ISA bus protocol
• ISA bus protocol supports standard I/O.
• The I/O address space is 16 bits, where it is 20 bits for memory.
• It uses compromise strobe/handshake control method.
• similar to memory protocol except address space.
ISA I/O bus read protocol

CYCLE C1 C2 WAIT C3 C4
CLOCK
D[7-0]
DATA
A[15-0] ADDRESS
ALE
/IOR
CHRDY

A basic memory protocol
D<0...7>
P0 Adr. 7..0 Data P0 D Q
A<0...15>
/CS
P2 Adr. 15…8 /OE
ALE G /WE
Q Adr. 7…0 74373 CS2 /CS1
8 HM6264
ALE P2
/WR /CS
/RD /RD
D<0...7>
/PSEN
A<0...14>
/OE
8051 27C256
• Interfacing an 8051 to external memory

– Ports P0 and P2 support port-based I/O when 8051 internal memory
being used.
– Those ports serve as data/address buses when external memory is
being used.
– 16-bit address and 8-bit data are time multiplexed; low 8-bits of
address must therefore be latched with aid of ALE signal.

A complex memory protocol
FSM description
Specification for a single read GO=0
operation
GO=1
CLK ADSP=1, ADSP=0,
S0 ADSC=1 ADSC=0 S1
/ADSP ADV=1, OE=1, ADV=0, OE=1,
Addr = ‘Z’ GO=0 Addr = Addr0
/ADSC
/ADV Data is
ready
addr <15…0> GO=0
GO=1 here!
/WE
/OE
ADSP=1, ADSP=1,
/CS1 and /CS2 ADSC=0 ADSC=1
S2 S3
ADV=1, OE=1, ADV=0, OE=0,
CS3 Addr = ‘Z’ GO=1 Addr = ‘Z’
data<31…0>
GO=1
GO=0
• Generates control signals to drive the TC55V2325FF memory chip in burst mode.
– Addr0 is the starting address input to device.
– GO is enable/disable input to device.

Interrupts (interrupt driven I/O)
• Servicing: read & process data from peripheral whenever it
has new data.
– Unpredictable
• Polling: MP repeatedly check for data
– Simple to implement
– Waste many clock cycles
• External interrupts
– Repeatedly MP checks Int pin after executing instruction, if
asserted => jump to ISR
– Pin polling?
• Into MP, done simultaneously with the exec. of Instr.
– Maskable vs Nonmaskable Interrupt
– Internal Interrupt (divide by 0,…)
– Software Interrupt .
Interrupt Addressing
• Fixed Int.: ISR address built in MP

• Vectored Int.:
– ISR address requested from peripherals by Inta pin
asserted by MP.
– The address stored in peripheral by extra register.
• Interrupt Address Table (compromise between
fixed & vectored)
– Table holds ISR addresses
– Peripherals provide entry number instead.
Fixed Int.
1. MP is executing its main program.
2. Peripheral_1 receives input data in a register and
assert Int to request servicing.
3. After completing Instr. Execution, MP detect
Int , saves current PC value and set PC = ISR
fixed address.
4. ISR reads Peripheral_1 data & processed it, then
deasserts Int.
5. ISR return, restoring PC and MP resume
execution.
Vectored Int.
Program memory μP
ISR
16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return

...
P1
Main program
...
PC
100: instruction
0x8000
101: instruction

DMA
• Buffering: temporary storage of data that is
awaiting processing.
• Using Interrupt:
– Storing & restoring MP states => consuming many
clock cycles (inefficient)
– No execution during data moving.
• I/O of DMA: separate single-purpose processor
(DMA controller).
– Purpose: transfer data between memories and
peripherals
DMA flow of actions
1. MP is executing its main program. It has already configured the
DMA ctrl registers.
2. Peripheral_1 receives input data in a register, and asserts req to
request servicing by DMA ctrl.
3. DMA ctrl asserts Dreq to request control of system bus.
4. After executing instruction, MP sees Dreq asserted, releases the
system bus, asserts Dack, and resumes execution. MP stalls only if
it needs the system bus to continue executing.
5. DMA ctrl asserts ack reads data and (b) writes that data to
memory.
6. DMA de-asserts Dreq and ack completing handshake with
Peripheral_1.
7. MP de-asserts Dack and resumes control of the bus.
8. Peripheral_1 de-asserts req.
DMA flow of actions (cont.)
Program memory
0x0000 0x0001
... Dack
Dreq
DMA ctrl P1
...
100: instruction
0x000 ack
PC
101: instruction 0x800 req 0x8000
1
10 0
0

Arbitration
• Multiple peripherals request service
simultaneously from single MP or single
DMA
• Arbitration: decide which one get services.
– Priority Arbiter.
– Daisy-Chain Arbitration.
– Network-Oriented Arbitration Methods.

Arbitration Priority Arbiter
– Is a single-purpose processor
– 2 schemes to determine priority among peripherals:
• Fixed priority: unique rank for each peripheral. Arbiter choose
the higher rank.
• Rotating priority (round-robin): based on history of servicing
(e.g. least recently serviced)
– More equitable of servicing.
MP System bus
7
Inta 5
Int Priority Peripheral1 Peripheral2

3 2
arbiter Ireq1
Iack1
2
Vectored Interrupt Ireq2

6
Iack2
246
Prof. (Dr.) Anil Rose
Arbitration Daisy-Chain Arbitration
• Peripherals connected as a chain
– Each peripheral has: req. output, ack. input, req. input, and ack. Output
• Add or remove peripherals without redesigning the system
• Peripherals at the end of chain could become intolerably slow.
• Isn’t supporting more advanced priority schemes
• If one peripheral stop, the other lose access
• Each peripheral must be daisy-chain aware
– Otherwise, external logic is used.
P
System bus
Peripheral1 Peripheral2
Inta
Ack_in Ack_out Ack_in Ack_out
Int Req_out Req_in Req_out Req_in 0

Arbitration Network-Oriented
– Multiple MP connected by a shared bus
(network).
– Arbitration among processors.
• Typically built right intoI the bus protocol
– The protocol must ensure that no contending
processors sending at the same time
– Examples: I2C, Ethernet, CAN …

Multilevel Bus Architectures
– Numerous type of communications:
• Most frequent and high speed (between MPs).
• Less frequent and low speed (between MP and Peripherals like
UART)
– Single high speed bus:
• Required each peripheral to have high-speed bus interface
– Extra gates ,Power consumption and cost.
• May not be very portable.
• May result in slower bus.
– 2 level buses:
• Processor local bus: connects MP, cache, memory controllers …
• Peripheral bus: ISA, PCI …
– emphasize portability, low power or low gate count.
• Bridge (single-purpose processor) connect two bus levels
Multilevel Bus Architectures cont.
– 2 level buses: VSI Alliance.
• Processor local bus
• System bus
• Peripheral bus
Micro- Cache Memory DMA
processor controller controller
Processor-local bus
Peripheral Peripheral Peripheral Bridge
Peripheral bus

Advanced Communication
Principles
– Physical layer: the medium that is used to carry
data from one device to another.
• Single wire, a set of wires, radio waves, or infrared
waves.
– Parallel communication
– Serial Communication
– Wireless Communication

Parallel communication
– Multiple data wires + control and possibly power
wires.
– Each wire carries one of the bits.
• High data throughput, if the length is short.
– Long parallel wires:
• High capacitance values => more time to charge or discharge
• Misalignment.
• Costly to construct.
• May be bulky
– In general, used when connect devices reside on the
same IC or circuit board.
Parallel Protocols
– PCI (Peripheral Component Interconnect)
• Originated at Intel 1990 and then administered by PCISIG
• First used in 1994
• For interconnecting chips, expansion boards, & processor memory
subsystem.
• Replaced ISA/EISA bus
• Transfer rate: 127.2 – 508.6 Mbit/s
• 32-bit addressing later extended to 64-bit
• Sync bus architecture
– ARM
• Designed by ARM Corporation
• Designed to interface with ARM line of processors.
• 32 data/address
• Sync data architecture
• Transfer rate not specified (function of the clock speed)
Serial communication
– Single data wire, along with control & possibly power
– Higher throughput than parallel when connect distant
devices
• Less average capacitance.
– Cheaper to build
– More complex interfacing logic & communication
protocols (compose & decompose data)
– Most protocols use same wire for control
• Start bit
• Stop bit
• May use additional wire for clocking purpose as sync tech.
Serial Protocols
– I2C (Inter-IC)
• Developed by Philips Semiconductors
• 2 wire bus protocol
• Connect peripheral ICs in electronic systems
• Transfer rate: up to 100 kbit/s, 7-bit address
• Fast mode: 3.4 Mbit/s, 10-bit address
• Flash, RAM, EPROM, Microcontrollers …
– CAN (Controller Area Network)
• For real-time application
• Developed by Robert Bosch GmbH to connect various components of car
• Over twisted pair of wires
• High integrated serial data communication
• Data rate up to 1 Mbit/s
• 11-bit addressing
• Documented in ISO 11898 & ISO 11519-2
• Common applications: Automobiles, elevator controllers, copiers, telescopes,
…
Serial Protocols
– FireWire (I-Link or Lynx)
• Developed by Apple Computer Inc.
• Specification is given by IEEE 1394
• Mass information transfer
• Transfer rate: 12.5 – 400 Mbit/s
• 64-bit addressing (64b net id, 6b node id, 48b mem addr)
• Real-time connection and disconnect and assignment (Plug
and Play)
• Designed for interfacing independent electronic devices.
– USB (Universal Serial Bus)
• Has 2 data rates: 12 Mb/s, 1.5 Mb/s
• For PC users to connect monitors, printers, scanners, …
• Used tiered star topology (USB hubs)
Wireless communication
– Physical layers:
• IR
– Relatively cheap
– Need line of sight
– Diode emits infrared light to generate signal, Infrared transistor
detects signal.
• RF
– Line of sight not necessary
– Longer distance communications
– Frequency hopping, to communicate while constantly changing
transmission frequency.

Wireless Protocols
– IrDA (Infrared Data Association)
• IrDA is an international organization
• Designed to support transmission between two devices over short-range point-to-point infrared.
• Rate: 9.6 Kb/s – 4 Mb/s
• Deployed in notebooks, printers, PDAs, cell phones,…
• MS Windows CE 1.0 the first Windows OS support it
• Available on several popular embedded OSs
– Bluetooth
• Use radio frequency
• Within 10 meters
• Doesn’t require a line-of-sight connection
– IEEE 802.11
• IEEE proposed standard for WLAN
• Ad-hoc vs. infrastructure
• PHY and MAC layers
• Data rate: 1Mbps, 2Mbps
• Calls: 2.4 – 2.4835 GHz frequency band (unlicensed band).
• Use CSMA/CA
• Signals for transmission: RTS, CTS, and ACK.

Reference
– “Embedded system Design: A unified
Hardware/Software Introduction”, Frank Vahid,
Tony Givarrgis, Wiley, 2002

Microcontrollers An Introduction Features & Applications

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MICROCONTROLLERS

Prof. (Dr.) Anil Kumar

Microprocessor: single chip processor

Prof. (Dr.) Anil Rose 3

More powerful processors Integrating all the

8,16, 32, & 64 bit MICROCONTROLLERS

Prof. (Dr.) Anil Rose 4

Cpu Data Bus(8)

Inter Face Peripheral

Prof. (Dr.) Anil Rose 5

Instruction decode &

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BUS activity for an opcode fetch cycle

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In 1976 Intel introduce the 8048 as the first single chip

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PART ON-CHIP ON-CHIP TIMERS

8031 0K 128 BYTES 2

8751 4K EPROM 128 BYTES 2

8052 8K ROM 256 BYTES 3

8032 0K 256 BYTES 3

8752 8K EPROM 256 BYTES 3

89c51 4K EEPROM 128 BYTES

PROGRAM STATUS WORD (PSW): This set of flags contains the

PORT 0 TO 3 LATCHES AND DRIVERS : These four

SERIAL DATA BUFFER: The serial data buffer internally

CONTRO; REGISTERS: the special function registers IP , IE ,

TIMING AND CONTROL UNIT: This unit drives all the

OSCILLATOR: this circuit generates the basic timing clock signal

EPROM AND PROGRAM ADDRESS REGISTER: these

SFR: this is a set of special function registers , which can be addressed

Opcode read from EPROM

ON-CHIP OSCILLATOR :- 8051 features an on

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• Mov Ro, #5FH , Mov A, @ Ro

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