Systemverilog: Professor: Sci.D., Professor Vazgen Melikyan

SystemVerilog
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

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SystemVerilog
Lecture - 5
Developed By: Vazgen Melikyan
1
OOP classes

SystemVerilog
Lecture - 5
2
Review, Class
 Class encapsulate class BusTran;
 Variables bit [31:0] addr, crc, data[8];

 Methods function void display;
 Class can be $display("BusTran: %h", addr);
endfunction : display
defined in
function void calc_crc;
 Program block crc = addr ^ data.xor;
 Module block endfunction : calc_crc
 Package endclass : BusTran

SystemVerilog
Lecture - 5
3
Review, Constructing object
program automatic;
myPacket p1=new();
myPacket p2;
initial begin
p2.encode=1’b0; // runtime Error
end class myPacket;
endprogram bit [2:0] header;
bit encode;
bit [2:0] mode;
bit [7:0] data;
bit stop;
endclass
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SystemVerilog
Lecture - 5
4
Review, This keyword
class Packet;
bit [31:0] addr;
function new (bit [31:0] addr);
this.addr = addr;
endfunction
endclass
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SystemVerilog
Lecture - 5
5
Review, Local class ABC;
byte public_var;
 Is available only to the local byte local_var;
methods of the same
class function void display();
 Is not accessible by child $display (public_var, local_var);
endfunction endclass
classes
 Nonlocal methods that module tb;
access local members initial begin ABC abc = new();
can be inherited and abc.display();
overridden by child class abc.public_var = 1;
abc.local_var = 1; //compilation error
end
endmodule
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SystemVerilog
Lecture - 5
6
Review, Static
class Packet;
bit [15:0] addr;
bit [7:0] data;
Static int ctr=0;
function new (bit [15:0] ad, bit

[7:0] d); addr = ad; data = d;
$display (addr, data);ctr++;
endfunction
endclass
module tb;
initial
begin Packet p1, p2, p3;
p1 = new (16'hdead, 8'h12);
p2 = new (16'hface, 8'hab);
p3 = new (16'hcafe, 8'hfc);
www.chipverify.com end endmodule
SystemVerilog
Lecture - 5
7
Constraints
Constraints use to generate random values that satisfy all conditions
class Pkt;
rand bit [7:0] addr;
randc bit [7:0] data;
constraint addr_limit { addr <= 8'hB; }
endclass
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SystemVerilog
Lecture - 5
8
rand
class Packet;
Can be used on rand bit [2:0] data; endclass
Normal variables
Arrays module tb;

Dynamic arrays
initial begin
Queues Packet pkt = new ();
run -all; for (int i = 0 ; i < 10; i++) begin
# KERNEL: itr=0 data=0x7 pkt.randomize ();
# KERNEL: itr=1 data=0x2
$display ("itr=%0d data=0x%0h", i,
# KERNEL: itr=3 data=0x1 pkt.data);
# KERNEL: itr=4 data=0x2 end
# KERNEL: itr=5 data=0x4 end
# KERNEL: itr=7 data=0x1 endmodule
# KERNEL: Simulation has finished. There
are no more test vectors to simulate. www.chipverify.com
SystemVerilog
Lecture - 5
9
Constraint example
class ABC;
rand bit [3:0] mode;
constraint c_mode { mode > 2; mode <= 6; };
endclass
module tb; ABC abc;

initial begin
abc = new();
for (int i = 0; i < 5; i++)begin

abc.randomize();
$display ("mode = 0x%0h", abc.mode);
end
end
endmodule
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SystemVerilog
Lecture - 5
10
Soft constraint
constraint c_data { soft data >= 4; ncsim> run
data <= 12; } abc = 0x4
… abc = 0x8
abc.randomize(); abc = 0x4
… abc = 0x7
abc = 0x7
abc.randomize() with { data == 2; };
…
ncsim: *W,RNDOCS: These variables contribute to

the set of conflicting constraints:
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SystemVerilog
Lecture - 5
11
Inheritance
class Packet; module tb;
int addr; Packet bc;
function new (int addr);
ExtPacket sc;
this.addr = addr; initial begin
endfunction bc = new
(32'hface_cafe);
function display (); bc.display ();
$display (addr);
endfunction
endclass sc = new
class ExtPacket extends Packet; (32'hfeed_feed,
int data; // only in child 32'h1234_5678);
function new (int addr, data); sc.display ();
super.new (addr); end
this.data = data;
endmodule
endfunction
function display ();
$display (addr, data);
endfunction
endclass
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SystemVerilog
Lecture - 5
12
Polymorphism
 Use of a variable of the base class type to

hold subclass objects and to reference the
methods of those subclasses directly from
the superclass variable
 Child class method to have a different
definition than parent class

SystemVerilog
Lecture - 5
13
Assign Child Class to Base Class
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SystemVerilog
Lecture - 5
14
Assign Child Class to Base Class (2)
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SystemVerilog
Lecture - 5
15
Assign Base Class to Child Class
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SystemVerilog
Lecture - 5
16
Assign Base Class to Child Class (2)
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SystemVerilog
Lecture - 5
17
Assign Base Class to Child Class (3)
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SystemVerilog
Lecture - 5
18
Virtual Methods
class Base;
rand bit [7:0] addr;

rand bit [7:0] data;
virtual function void

$display(string tag="Thread1");
$display (tag, addr, data);
endfunction
endclass
class Child extends Base;
rand bit en;
function void display(string tag="Thread1");
$display (tag, addr, data, en);
endfunction
endclass
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SystemVerilog
Lecture - 5
19
Virtual Methods
Virtual function can change inside child class
and called as child method
// base handle pointed to sub class handle

bc = sc;
// This calls the display() in base class

bc.display ();
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SystemVerilog
Lecture - 5
20
Without virtual keyword
class Packet;
int addr;
this.addr = addr;
endfunction
function void display ();

$display (addr);
endfunction module tb;
Packet bc;
endclass ExtPacket sc;
initial begin
sc = new (32'hfeed_feed, 32'h1234_5678);

bc = sc; bc.display ();
end
www.chipverify.com endmodule
SystemVerilog
Lecture - 5
21
With virtual keyword
class Packet;
int addr;
this.addr = addr; endfunction
virtual function void display ();

$display (addr);
endfunction
module tb;
endclass Packet bc;
ExtPacket sc;
initial begin
sc = new (32'hfeed_feed, 32'h1234_5678);
bc = sc; bc.display ();
end
endmodule
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SystemVerilog
Lecture - 5
22
Static functions
 Can be called outside the class

 Has no access to non-static members
 Cannot be virtual
 Call scope through operator ::

SystemVerilog
Lecture - 5
23
Static function (1)
class Packet;
static int ctr=0;
function new ();
ctr++; endfunction
static function get_pkt_ctr ();

$display ("ctr=%0d", ctr);
endfunction
endclass
module tb;
Packet pkt [6];
initial begin
for (int i = 0; i < $size(pkt); i++)
pkt[i] = new;
Packet::get_pkt_ctr(); // Static call
pkt[5].get_pkt_ctr(); // Normal call
end
endmodule
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SystemVerilog
Lecture - 5
24
Static function (2)
class Packet;
static int ctr=0;
bit [1:0] mode;
function new ();
ctr++;
endfunction
static function
get_pkt_ctr ();
$display ("ctr=%0d mode=%0d", ctr, mode);
endfunction
endclass
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SystemVerilog
Lecture - 5
25
Shallow and Deep Copy
Shallow copy
Packet pkt, pkt2;
pkt = new;
pkt2 = new pkt;
Deep copy
Packet p1 = new;
Packet p2 = new;
p2.copy (p1);
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SystemVerilog
Lecture - 5
26
Shallow copy
class Header;
int id;
function new (int id);
this.id = id;
endfunction
function showId();
$display ("id=0x%0d", id);
endfunction
endclass
class Packet;
int addr;
int data;
Header hdr;
function new (int addr, int data, int id);
hdr = new (id);
this.addr = addr;
this.data = data;
endfunction
function display (string name);
$display ("[%s] addr=0x%0h data=0x%0h id=%0d", name, addr, data,
hdr.id);
endfunction
endclass
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SystemVerilog
Lecture - 5
27
Shallow copy (2)
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SystemVerilog
Lecture - 5
28
Deep copy
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SystemVerilog
Lecture - 5
29
Parameterized Classes
class something #(int size = 8);
bit [size-1:0] out;
endclass
module tb;
something #(16) sth1; // pass 16 as "size"
something #(.size (8)) sth2; // pass 8 as "size"
typedef something #(4) td_nibble; // create an alias
td_nibble nibble;
initial begin
sth1 = new;
sth2 = new;
nibble = new;
$display ("sth1.out = %0d bits", $bits(sth1.out));
$display ("sth2.out = %0d bits", $bits(sth2.out));
$display ("nibble.out = %0d bits", $bits(nibble.out));
end
endmodule
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SystemVerilog
Lecture - 5
30
Pass datatype as a parameter
class stack #(type T = int);
T item;
function T add_a (T a);
return item + a;
endfunction
endclass
module tb;
stack st;
stack #(bit[3:0]) bs;
stack #(real) rs;
initial begin
st = new; bs = new; rs = new;
st.item = -456;
$display ("st.item = %0d", st.add_a (10));
bs.item = 8'hA1;
$display ("bs.item = %0d", bs.add_a (10));
rs.item = 3.14;
$display ("rs.item = %0.2f", rs.add_a (10)); end
endmodule
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SystemVerilog
Lecture - 5
31
Extern keyword
class ABC;
extern function void display();
endclass
function void ABC::display();

$display ("Hello world");
endfunction
module tb;
initial begin
ABC abc = new();
abc.display();
end
endmodule
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SystemVerilog
Lecture - 5
32

Systemverilog: Professor: Sci.D., Professor Vazgen Melikyan

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Systemverilog: Professor: Sci.D., Professor Vazgen Melikyan

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SystemVerilog

Professor: Sci.D., Professor

Synopsys University Courseware

Synopsys University Courseware

 Class encapsulate class BusTran;

 Variables bit [31:0] addr, crc, data[8];

 Package endclass : BusTran

Synopsys University Courseware

function new (bit [31:0] addr);

function new (bit [15:0] ad, bit

constraint addr_limit { addr <= 8'hB; }

Arrays module tb;

module tb; ABC abc;

for (int i = 0; i < 5; i++)begin

ncsim: *W,RNDOCS: These variables contribute to

 Use of a variable of the base class type to

Synopsys University Courseware

rand bit [7:0] addr;

virtual function void

// base handle pointed to sub class handle

// This calls the display() in base class

function void display ();

virtual function void display ();

 Can be called outside the class

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static function get_pkt_ctr ();

Packet pkt, pkt2;

extern function void display();

function void ABC::display();

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