DAC Interfacing

V ref
D Q

D Q DAC V out
CPU

Clock
Address
bus Address
decoder

IOW
AEN
 IBM – PC Ports
Data bus
R/W MEMR

IO/M MEMW
DEN
DEN IOR
IOW
ALE
OUT DX,AL
OUT DX,AX
Address bus

300H - 31FH For prototype Cards

AEN=0 For I/ O ports A9 A5 A4 A1 A0

AEN=1 For DMA For Card For Port For Byte
Selection Selection Selection
 Address Decoder
FH 31 – 300
IOR

A1 IN 300H
A5 A2
IN 302H
A3
A6 decoder A4
IN 304H

A7
decoder

A1 OUT 300H
A2
A3 OUT 302H
A4 OUT 304H
A9 A8 AEN

IOW
Mov Cx, count
OUT Dx, AL *

Mov AL, SI
“LODSB” For 10- bit
”OUT DX,AX“
INC SI Or
”LODSW“ or 12- bit
DAC
DEC CX
“LOOP * ”
* JNZ

Mov BL , M

”Delay to adjust “ Ts DEC BL**

** JNZ
D0 D0

D1 D1

D2 D2 V out
bit – 10
D7 D7
DAC
D0 D8

D1 D9 A0 CE

A0
OUT 300H
 A0
OUT DX,AX

D0
D1
D2
D3 DAC
D4
D5
D6
D7

D0
D1

A0 OUT DX,AX
 V ref

VIN
ADC
data
CPU
bus

Start IN 300H
END

OUT DO
302H

IN 302H
OUT 302H, AL **
IN AL, 302 H *
AND AL, 1
* JNZ
IN AL, 300H
STOSB

** LOOP

Delay to adjust Ts
Start

End

interrupt
V cc INTR
D Q
End Elk
clr CPU
Int. service routin
OUT 304H, AL
Out 304 H
IN AL, 300H
STOSB
OUT 302H, AL
IRET
IN AX, 300H
B0 D0
STOSW B1 D1

bit-10
V in
ADC B 7 D7
B0 D0
B1 D1

A0

OE

A0 IN 300H