FinFET TECHNOLOGY

J.Krishna chaithanya
HT.NO : 17K41A0440
OUTCOMES:

•Understanding the fundamental differences between mosfet and finfet

technology.
•To understand the working of a finfet.
•To know the key challenges in building a finfet.
•To know the importance of finfet and its applications.
• To understand the role of finfet in semi conductor industries.
MOSFET Vs FinFET
•Mosfet is a planar transistor used in standalone applications like amplifier, switch,
building storage devices.

•Finfet is a non planar dual gate transistor used in silicon architecture to improve
computational density over traditional designs.

•As the transistor size is decreasing day by day the leakage currents are
increasing between source and the drain terminals (< 90nm transistors).

•This leakage currents are due to less control of gate terminal over the channel and
very less gap between the source and drain.

•So there is a need of transistor that has high control over the channel and on the
other hand it should occupy very less space ,finfet solves this purpose.
WORKING OF FinFET
WORKING:

•Unlike mosfet the finfet has more control over the channel.

•The channel is surrounded by the gate terminal.

•When the gate terminal is energized the region of the fin located beneath the
electrode is inverted and forms a conductive path between source and the drain.

•Although the finfet is a depleted device most of the conduction occurs on the
outer edge if the fin.
Why finfets are better than mosfet ?
Challenges in making FinFET:
Corner effect
KEY CHALLENGES:

•More complex non planar design

•Parasitic capacitances

•Corner effect

•Quantum confinement effects(as we go on decreasing the size of transistor.)

 Applications:
• Efficient processors and SOC (system on chip) manufacturing.
• Low power consuming chips used in PC,mobiles,ASIC(application
specific integrated circuits)
• less costlier, compact and faster computational capable chips.
Recent advancements:
• Intel 22nm FinFET (22FFL) Process Technology for RF and mm
Wave Applications and Circuit Design Optimization for FinFET
Technology
• A 16nm FinFET CMOS technology for mobile SOC and computing
applications
• A 7nm FinFET technology featuring EUV patterning and dual strained
high mobility channels
References:
1. https://ieeexplore.ieee.org/abstract/document/8614490
2. https://ieeexplore.ieee.org/abstract/document/6724591
3. https://ieeexplore.ieee.org/abstract/document/1242886
4. https://ieeexplore.ieee.org/abstract/document/7838334
5. http://www.maltiel-consulting.com/FinFET-Layout-Design.html
THANK YOU