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BRAIN:-
“THE CPU WAS BORN TO SOLVE PROBLEMS THAT DIDN’T
EXISTED BEFORE”
OBJECTIVES
CU
ALU{short for
{short for arithmetic Registers
control logic}
unit}
MBR←<MAR>
IR←MBR
How instruction is decoded by the processor ?
Earlier we discussed about Instruction fetch, we wrote “then
decode the opcode”.
It is common to talk of the fetch-execute cycle, it is useful to think
about decoding as a separate distinct phase in a fetch-decode-
execute cycle.
. We had a mechanism of producing a set of level
signal[LDA=1,STA=0,ADD=0 etc] when the opcode is LDA; and
similarly for other opcode; and
. We have written the RTL for all the execute
phases, and known that the execute phase
start at control steos 10,13,15,18.
EXECUTION OF COMMAND
• Depending on the architecture of CPU, there may be a single action or a
sequence of actions Performed.
• During every action various parts of CPU are enabled or disabled so they
can perform all or part of the desired operation.
• Typically these actions are completed in Split of a second.
• The number of Cores (unique CPU) tells us computational power of CPU.
Storing
◦ The Result of execution is stored back to memory for later retrieval, if
requested again.
◦ Registers are the memory location where the results are stored for quick
access.