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Embedded

Chapter 3: System Design,


Bahria University
BRANCH, CALL, AND Islamabad
TIME DELAY LOOP
“PIC Microcontroller and Embedded Systems”, Muhammad
Ali Mazidi, Rolin D. Mckinlay, Danny Causey Prentice Hall,
2008.

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SECTION 3.2:
CALL INSTRUCTIONS AND
STACK

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• Control transfer instruction which is used to call a
subroutine,
• Subroutines are often used to perform task that need
to be performed frequently.
• This makes program more structured in addition to
saving memory space.
CALL • In PIC18 there are two instructions for call CALL (long
Instructions call) and RCALL (relative call)

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• CALL instruction
It is 4-byte (32-bit) instruction
The 12-bits are used for the opcode and the other
20 bits, A21-A1 are for address of the target
subroutine.
Like GOTO instruction, the lowest bit of PC is 0
CALL CALL can used to call subroutines located
anywhere within the 2M address

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• To make sure that PIC knows the where to come back
to after execution of the called subroutine
• PIC saves on the address of the instruction
immediately below the CALL instruction in the stack
• when the subroutine is called, control is transferred to
that subroutine, and the processor saves the PC on the
CALL stack and begins to fetch instruction the new location.
• After finishing execution of the subroutine, the
instruction RETURN transfers control back to the caller.
• Every subroutine needs RETURN as the last instruction

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• Stack and Stack pointer (SP)
It is read/write memory (RAM)
Used to store some very critical information
temporarily.
This information is usually an address, but could be
Stack and data as well
Stack
pointer

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• Stack and Stack pointer (SP)
The stack in PIC18 is 21-bit because PC is 21-bit it
can take values of 00000 to 1FFFFFh
SP (stack pointer) register is used to access the
stack
Stack and SP is 5-bit pointer takes values of 00-1FH gives
total of 32 location where each location is of 21-
Stack bits
pointer

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• Stack and Stack pointer (SP)
At power up, the SP register contains value 0
This means the stack location 1 is the first location
used for the stack the SP points to the last-used
location.
Stack and The location 0 of the stack in not available and we
have only 31 stack locations in PIC18
Stack
pointer

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• PUSH: to store CPU information such as the PC on the
stack in called PUSH
• POP: to loading the content of the stack back into a
CPU register is called a POP
How stacks
are
accessed in
PIC18

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• Pushing onto the stack
SP pointing to the last used location of stack
Last-used location is referred to as top of the stack
(TOS)
When data is pushed onto the stack, SP is
Pushing incremented
and • Popping form the stack
Popping It is opposite of pushing
from stack When the RETURN instruction at the end of
subroutine is executed, top location value of the
stack is copied back to PC and SP is decremented
once.
The stack is LIFO (Last-In-First-Out) memory

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• CPU uses the stack to save the address of the
instruction just below the CALL
• This is how CPU knows where to resume when return
from the subroutine
CALL
instruction
and role of
the stack

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CALL
instruction
and role of
the stack

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CALL
instruction
and role of
the stack

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• In PIC18 there are only 31 RAM locations for the stack
and they are mapped to addresses 01 to 1FH
• Stack is used for calls and interrupts

Upper limit
of the stack

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• It is used to make modules of the large program and
assign each modules to different programmers in
order to shorten development time
Calling
many
subroutine
form the
main
program

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• RCALL (relative call)
It is 2-byte instruction in contrast to CALL, which is
4-byte
5-bits OPCODE and 11-bits for the relative address
The target address must be within in 2K because
RCALL 11-bit are used for the address
(relative No difference between RCALL and CALL in term of
saving PC value and function of RETURN
call) The only difference is that target address for CALL
in anywhere in 2M where in RCALL must be within
a 2K range
RCALL instead of CALL can save several bytes of
Program ROM space

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RCALL
instruction

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SECTION 3.3:
PIC18 TIME DELAY AND
INSTRUCTION PIPELINE

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• Two factor that affect the accuracy of the time delay
using Assembly language
1. The crystal frequency :the frequency of the
crystal oscillator connected to the OSC1 and
Delay OSC2 input. The Duration of the clock period for
calculation the instruction cycle is a function of this crystal
2. The PIC design: advance in IC technology and CPU
for the design have made the single instruction cycle a
PIC18 common feature µC. There are three ways to do
it
a) Use Harvard architecture to fit the maximum amount of code
and data into the CPU
b) Use RISC architecture features such as fixed-size instructions
c) Use of pipeline to overlap fetching and execution of the
instructions

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• Pipelining
In early microprocessors CPU had to fetch an
instruction from memory, then execute it, and then
fetch the next instruction.
The idea of pipelining in its simplest form is to
allow the CPU to fetch and execute at the same
time
Pipelining

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• Instruction cycle time for the PIC
It take certain amount of time for the CPU to
execute an instruction. In PIC, this time is referred
to as instruction cycle
In the PIC18 instructions are either 2-byte or 4-
Instruction byte, so most of instructions take no more than
cycle time one or two instruction cycle to execute
for the PIC In the PIC family, the length of the instruction cycle
depends on the frequency of the oscillator
connected to the PIC system
In PIC18, one instruction cycle consists of four
oscillator periods( 1 instruction cycle=4 oscillator
period)

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• To calculate the time of instruction cycle for the PIC,
we take ¼ of the crystal frequency, then take its
inverse.
• Or take inverse of the frequency (T=1/f) and multiply it
by 4.
Instruction
cycle time Time of 1 instruction = 4 * (time period of oscillator)
for the PIC Clock Frequency = 1 MHz
Time period = 1 micro second
1 machine cycle = certain number of clock cycles
1 machine cycle = 4 clock cycles
Instruction execution is measured in terms of machine cycles
Instruction is executed in 2 machine cycles = 8 clock cycles
Time = 8 micro second
Clock frequency => clock time
Machine cycle = how many clock cycles
Time for 1 machine cycle =
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Instruction
cycle time
for the PIC

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• Branch penalty
The overlapping of fetch and execution is widely used
in µC
For concept of pipelining to work, we need Buffer or
queue in which an instruction is prefetched and ready
to executed.
Branch In some circumstances, the CPU must flush out the
queue(i.e) in branch instruction, the CPU starts to fetch
penalty codes from the new memory location. Code that was
previously fetched is discarded
In this case, the execution unit must wait until the
fetch unit fetches the new instruction. This is called
branch penalty
This means majority of PIC instruction take one cycle ,
some instruction take two or three instruction cycles.
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• GOTO , BRA, CALL and all the conditional branch
instruction such as BNZ, BC and so on, can take two or
three instruction cycles if branched
• The conditional branch instruction can take only one
instruction cycle if it does not jump
• For BNZ
Branch If Z=0, will jump and that takes two instruction
penalty cycle.
If Z=1 then it falls through and takes only one
instruction cycle

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Delay
calculation
for PIC18

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Time period of clock = 0.25 Micro second
Time period of instruction/machine cycle

Delay
calculation 255

for PIC18
No. of instruction cycles = 1+1+(1
Time of execution = 1278*1 micro

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Delay
calculation
for PIC18

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Delay
calculation
for PIC18

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Delay
calculation
for PIC18

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Delay
calculation
for PIC18

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Delay
calculation
for PIC18

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END
CHAPTER 3

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