HYBRID ADDER DESIGN USING

ITERATIVE AND KOGGE STONE

ADDERS
 AGENDA
• INTRODUCTION TO ADDERS • BLOCK DIAGRAM DESCRIPTION
• AIM • PROPOSED ITERAIVE
ALGORITHM
• DEFECTS IN EXISTING MODEL
• RESULTS AND DISCUSSION
• EXISTING MODEL
• TABULATIONS
• PROPOSED MODEL BLOCK • ADVANTAGES AND
DIAGRAM DISADVANTAGES
• FLOW DIAGRAMS • CONCLUSIONS
 INTRODUCTION TO ADDERS
• Today’s VLSI designs demand high speed, low power and reasonably good Figure of Merit adders with minimum
area penalty.
• Adders are the basic building blocks of Arithmetic and Logic Units (ALUs) which form the important component of
processors in all system designs.
• Optimizing the important parameters such as Power, Speed and Area, inherently enhances the performance of the
VLSI system under design.
• Of the several optimization methods available, Circuit Level Optimization and Logic Level Optimization are
slightly predominant.
• Design, performance analysis and comparison of power consumption has been performed for 4 adders – the Ripple
Carry Adder, the Kogge Stone Adder, the Carry Skip Adder and the Brent Kung Adder, each being a 16-bit adder.
• The Leakage Power, Dynamic Power and the Total Power consumed by these adders have been estimated
 AIM
• TO IMPROVISE A NOVEL ADDER VIA ITERATIVE APPROACH TO
INITIATE BETTER PERFORMANCE CHARACTERISTICS
(AREA,POWER AND DELAY)
 PROBLEMS IN EXISITNG DESING
• HIGH AREA WITH 8BIT AND 16 BITS DESIGN USING KOGGE
STONE AND ARRAY ADDERS
• LESS ACCURACY ON THE DESIGN STRUCTURE
• DELAY AND POWER EFFICENCY IS POOR
CARRY SAVE ADDER 4 BIT
 EXISITING ADDERS
• CARRY SAVE
ADDERS
• KOGGE STONE
ADDERS
• Pre processing: This step involves computation of generate and propagate
signals corresponding too each pair of bits in A and B. These signals are
given by the logic equations below:

• Carry look ahead network :This block differentiates KSA from other
adders and is the main force behind its high performance.
 KOGGE STONE ADDER
• This step involves computation of carries corresponding to each bit. It uses group propagate and
generate as intermediate signals which are given by the logic equations below:

• Post processing This is the final step and is common to all adders of this family (carry look ahead).
It involves computation of sum bits. Sum bits are computed by the logic given below:
PROPOSED MODEL
 DESCRIPTION
• Each model of the parallel adder is implemented with the accordance to
initiate the different set of input changes via 8,16,32 simultaneously.
• The proposed iterative model encapsulates the different inputs from the
kogge stone and array adders for providing the iterative adding model.
• The input changes are depicted with width changes as mentioned in circuit
diagram which can be modelled with higher stages like 64,128 and 256.
 ITERATIVE ALGORITHM FLOW
DIAGRAM
• Each design blocks from the adder are
combined with iterative loop model
initiating the different outputs observed
at each stages of adder.
• This approach improvises on the
reduction of partial products and
improved accuracy of the sum and
carry generations.
RESULTS AND DISCUSSION
TABULATIONS
 ADVANTAGES
• MORE STABLE STRUCTURE DESIGN USING HYBRID MODEL
• IMPROVED AREA, POWER AND DELAY PERFORMANCE FOR
HYBRID MODEL
 DISADVANTAGE
• DELAY WILL CHANGE ABRUPTLY WHEN N>256.
 CONCUSIONS
• The proposed model is modelled with 8bit,16 –bit and32 bit Adders –
Kogge Stone Adder and Carry SAVE Adder and hybrid adders have
been designed.
• Power reports have been generated for each of them, using RTL Synthesis
tool.
• From the results it is observed that total power decreases as technology is
reduced