ABSTRACT

• Inexact (or approximate) computing is an attractive paradigm for digital

processing at Nano-metric scales. Inexact computing is particularly
interesting for computer arithmetic designs.
• Our proposed model improvises on 16 x 16 and 8x8 multiplier design.
• These designs rely on different features of compression, such that
imprecision in computation (as measured by the error rate and the so-called
normalized error distance) can meet with respect to circuit-based figures of
merit of a design (number of transistors, delay and power consumption).
• Two different schemes for utilizing the proposed approximate compressors
are proposed and analyzed for a proposed approximate multiplier can
achieve both low power and high accuracy.
SIGNIFICANCE
Significance Driven Logic Compression.
• According to the significance, different weights use different compressors (i.e., counters) to
accumulate their product terms.
• The higher significance weights use accurate 4:2 compressors, the middle significance
weights use near-accurate compressors, and the lower significance weights use inaccurate
compressors. As a result, the power consumption can be reduced with a small error.
High Order Approximate Compression.
• For the middle significance weights, we use high-order approximate compressors (e.g., 8:2
compressor) to reduce the logic of carry chains. As a result, both the delay and the power
can be greatly saved.
• To the best of our knowledge, the proposed design is the first work that utilizes high-order
approximate compressors in the approximate multiplier design.
EXSITING MODEL
• Carry Model For 5:2 Compressor:
• The Approximation of Sum Here,
we study the approximation of the
logic of Sum output.
• Conventionally, the tree of XOR
gates are used to produce the
output Sum.
• However, compared with other
logic gates, XOR gate often has
larger design overheads. We use
the logic gates in SAED 32nm cell
Figure 1: Representing the carry model for 5:2 compressor
library as an example. Table tabulates the comparisons among
OR gate, NOR gate, XNOR gate, and XOR gate.
• The existing design ensures the
design with 5:2 compressor
design with sum and carry
equations with the logical
elements mention in figure 2. For
accurate and exact scenario XOR
is replaced with XNOR and OR is
replaced with NOR.

Figure: Sum of 5:2 compressor. (a) Accurate (b) Our

approximate.
COMPRESSORS AND ITS
FORMULATION
Proposed Higher order compressor 7:3:
• The above design model for 7:3 is comprised
with a four set of 3:2 compressor and single
4:2 with two 3:2.Each set of structure is
observed with the no of inputs are consider as
the requirement.
• 1. Incase of 4:2 and 3:2 we have only two 3:2
models are connected with one 4:2 model.
• 2. Similarly for one 6:3 and one 3:2 model is
required for implementing the 7:3 compressor.
….CONTD
• The speed of addition is limited due to the
time taken by the carry signal to propagate
through the adder.
• The approx. regular adder was introduced to
mitigate the problem of carry propagation
delay by independently generating multiple
carries and then selecting the correct sum
and carry outputs depending on the value of
previous carry.
• As previously discussed, this type of was not
area efficient due to the use of pair of Adder
structure to impart the design capabilities to
produce the final sum and carry output.
….CONTD
A new approximate adder is presented. This adder operates
on a set of pre-processed inputs. The input pre-processing
(IPP) is based on the interchange-ability of bits with the same
weights in different addends. For example, consider two sets
of inputs to a 4-bit adder:
i)A= 1010,B= 0101and
ii)A= 1111,B= 0000.
Clearly, the additions of i) and ii) produce the same result. In
this process, the two input bits AiBi= 01are equivalent
toAiBi= 10(with i being the bit index), because of the
interchangeability of the corresponding bits in the two
operands.
….CONTD
• The basic rule for the IPP is to switch Ai
and Bi if Ai= 0andBi= 1(for an yi), while
keeping the other combinations
(i.e.,AiBi= 00,10and11) unchanged. By
doing so, more1’s are expected in Aand
more0’s are expected in B. If ̇Ai ̇Bi are
the ith bits in the pre-processed inputs,
the IPP functions are given by:
• A_x=A_i+ B_i.. (1)
• A_xi=A_i* B_i.. (2)
RESULTS AND DISCUSSION
• As per the design criteria we
have observed a direct variation
of the simulated values from the
input changes from the values of
• 1. 12 and 6
• 2. 10 and 10
• 3. 10 and 15
• Each set of values are
representing one of the approx.
and accurate design ensuring
the as per the design approach.
COMPARISON TABLE
CONCLUSION
• A novel approximate multiplier design is proposed using a newly
designed approximate adder.
• On a statistical basis the proposed multiplier has a very small error
distance and thus a high accuracy.
• Simulations have shown that the proposed design has a shorter
critical path delay and a significantly lower power consumption
compared to an exact compressor multiplier.
• It also uses a configurable error recovery that can produce more
accurate results than other state-of-the-art approximate multipliers.
ADVANTAGES AND SCOPE
• The power saving may be increased if the following criterion is
considered in the future low power VLSI design.
• Number of bits considered may be increased in the encoding
scheme
• Power can be reduced by improving the partial product compression
ratio.